alt_rvp.mdwn

   1 # Lanes
   2
   3 The term "Lanes" is borrowed from Hwacha (and is an implementation
   4 detail not an actual part of the ISA)
   5
   6 Register table
   7
   8 | reg num | Lane 0 | Lane 1 | Lane 2 | Lane 3 |
   9 | ------- | ------ | ------ | ------ | ------ |
  10 | r0      | (31.0) | (31.0) | (31.0) | (31.0) |
  11 | r1      | (31.0) | (31.0) | (31.0) | (31.0) |
  12 | r2      | (31.0) | (31.0) | (31.0) | (31.0) |
  13
  14 Example parallel add:
  15
  16     /* XLEN and N are "baked-in" to the hardware */
  17     parameter XLEN;
  18     parameter N;
  19     /* note that N cannot be greater than XLEN */
  20
  21     register plane[XLEN];
  22     register x[N][32][XLEN];
  23
  24     function op_add(rd, rs1, rs2) {
  25        /* note that this is ADD, not PADD */
  26        int i;
  27        for (i = 0; i<N; i++)
  28           if (plane[i])
  29              x[i][rd] <= x[i][rs1] + x[i][rs2];
  30     }
  31     /* note that "<=" is the Verilog non-blocking assignment operator */
  32