alt_rvp.mdwn

   1 # Lanes
   2
   3 Register table
   4
   5 | reg num | Lane 0 | Lane 1 | Lane 2 | Lane 3 |
   6 | ------- | ------ | ------ | ------ | ------ |
   7 | r0      | (31.0) | (31.0) | (31.0) | (31.0) |
   8 | r1      | (31.0) | (31.0) | (31.0) | (31.0) |
   9 | r2      | (31.0) | (31.0) | (31.0) | (31.0) |
  10
  11 Example parallel add:
  12
  13     /* XLEN and N are "baked-in" to the hardware */
  14     parameter XLEN;
  15     parameter N;
  16     /* note that N cannot be greater than XLEN */
  17
  18     register plane[XLEN];
  19     register x[N][32][XLEN];
  20
  21     function op_add(rd, rs1, rs2) {
  22        /* note that this is ADD, not PADD */
  23        int i;
  24        for (i = 0; i<N; i++)
  25           if (plane[i])
  26              x[i][rd] <= x[i][rs1] + x[i][rs2];
  27     }
  28     /* note that "<=" is the Verilog non-blocking assignment operator */
  29