alt_rvp.mdwn

   1 # Lanes
   2
   3 Example parallel add:
   4
   5     /* XLEN and N are "baked-in" to the hardware */
   6     parameter XLEN;
   7     parameter N;
   8     /* note that N cannot be greater than XLEN */
   9
  10     register plane[XLEN];
  11     register x[N][32][XLEN];
  12
  13     function op_add(rd, rs1, rs2) {
  14        /* note that this is ADD, not PADD */
  15        int i;
  16        for (i = 0; i<N; i++)
  17           if (plane[i])
  18              x[i][rd] <= x[i][rs1] + x[i][rs2];
  19     }
  20     /* note that "<=" is the Verilog non-blocking assignment operator */
  21