cole.mdwn

   1 # Cole Poirier
   2
   3 Former Apprentice at Libre-SOC
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
   6
   7 # Status tracking
   8
   9 move things along from one stage to the next
  10
  11 ## Currently working on
  12
  13 - Reach out to lu_zero of Gentoo about SV POWER binutils
  14 - <https://bugs.libre-soc.org/show_bug.cgi?id=486> Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page
  15 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  16   - shared with lkcl
  17 - <https://bugs.libre-soc.org/show_bug.cgi?id=484> Write VHDL to expose CR and XER from Microwatt so single-stepping is possible
  18   - shared with lkcl
  19 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> Create I-Cache from microwatt icache.vhdl
  20   - shared with lkcl
  21 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> Create D-cache from microwatt dcache.vhdl
  22   - shared with lkcl
  23 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create MMU from microwatt mmu.vhdl
  24   - shared with lkcl
  25 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
  26 - <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
  27 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
  28 - <https://bugs.libre-soc.org/show_bug.cgi?id=388> bpermd tutorial
  29 - <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG
  30 - <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
  31 - <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
  32
  33 ## List of things that need more fleshed out bug reports:
  34
  35 - Scoreboard documentation
  36   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
  37
  38
  39 - LDST documentation
  40   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
  41
  42
  43 ## Completed but not yet submitted
  44
  45 ## Submitted for NLNet RFP
  46
  47 submitted but not confirmed paid:
  48
  49 ## Paid
  50
  51 ### MOU coriolis2 2019-10-029, received payment on 2021-MAY-5
  52
  53 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> determine SRAM block size and implement it
  54   - EUR 50
  55
  56 ### MOU wishbone 2019-10-043, received payment on 2021-MAY-5
  57
  58 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI JTAG TAP needed
  59   - EUR 150
  60
  61 ### MOU coriolis2 2019-10-029, received payment on 2020-DEC-20
  62
  63 - <https://bugs.libre-soc.org/show_bug.cgi?id=178> Coriolis2 tutorial
  64   - EUR 500
  65
  66 ### MOU wishbone 2019-10-043, received payment on 2020-OCT-01
  67
  68 - <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
  69   - EUR 150
  70
  71 - <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
  72   - EUR 100
  73
  74 - <https://bugs.libre-soc.org/show_bug.cgi?id=472> Tutorial and dev page needed for mesa driver
  75   - EUR 100
  76
  77 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe discussion
  78   - EUR 500. shared. lkcl (60%, EUR 300), cole (20%, EUR 100), samuel (20%, EUR 100)
  79
  80 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
  81   - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
  82
  83 ### MOU coriolis2 2019-10-029, received payment on 2020-OCT-01
  84
  85 - Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
  86   - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
  87   - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
  88   - <https://bugs.libre-soc.org/show_bug.cgi?id=320>