bug 1244: separate frame for linked list image
[libreriscv.git] / conferences / fosdem2024 / fosdem2024_ddffirst / fosdem2024_ddffirst.tex
1 \documentclass[slidestop]{beamer}
2 \usepackage{beamerthemesplit}
3 \usepackage{graphics}
4 \usepackage{pstricks}
5 \usepackage{pgffor}
6 \usepackage{listings}
7
8 \graphicspath{{./}}
9
10 \title{Data-Dependent-Fail-First}
11 \author{Luke Kenneth Casson Leighton and Shriya Sharma}
12
13
14 \begin{document}
15
16 \frame{
17 \begin{center}
18 \huge{The Libre-SOC Hybrid 3D CPU}\\
19 \vspace{32pt}
20 \Large{Data-Dependent-Fail-First}\\
21
22 \vspace{24pt}
23 \Large{FOSDEM2024}\\
24 \vspace{16pt}
25 \large{Sponsored by NLnet's PET Programme}\\
26 \vspace{6pt}
27 \large{\today}
28 \end{center}
29 }
30
31
32
33 \begin{frame}[fragile]
34 \frametitle{Simple-V CMPI in a nutshell}
35
36 \begin{semiverbatim}
37 function op\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
38 (assuming you know power-isa)
39  int i, id=0, ira=0;
40  for (i = 0; i < VL; i++)
41   CR[BA+id] <= compare(ireg[RA+ira], SI);
42 if (reg\_is\_vectorised[BA] ) \{ id += 1; \}
43 if (reg\_is\_vectorised[RA])  \{ ira += 1; \}
44 \end{semiverbatim}
45
46 \begin{itemize}
47 \item Above is oversimplified: predication etc. left out
48 \item Scalar-scalar and scalar-vector and vector-vector now all in one
49 \item OoO may choose to push CMPIs into instr. queue (v. busy!)
50 \end{itemize}
51 \end{frame}
52
53
54 \frame{\frametitle{Load/Store Fault-First}
55
56 \begin{itemize}
57 \item Problem: vector load and store can cause a page fault
58 \item Solution: a protocol that allows optional load/store
59 \item instruction \textit{requests} a number of elements
60 \item instruction \textit{informs} the number actually loaded
61 \item first element load/store is not optional (cannot fail)
62 \item ARM SVE: https://arxiv.org/pdf/1803.06185.pdf
63 \item more: wikipedia Vector processor page: Fault/Fail First
64 \vspace{10pt}
65 \item Load/Store is Memory to/from Register, what about
66 Register to Register?
67 \item Register-to-register: "Data-Dependent Fail-First."
68 \item Z80 LDIR: Mem-Register, CPIR: Register-Register
69 \end{itemize}
70 }
71
72 \begin{frame}[fragile]
73 \frametitle{Data-Dependent-Fail-First in a nutshell}
74
75 \begin{semiverbatim}
76 function op\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
77 int i, id=0, ira=0;
78 for (i = 0; i < VL; i++)
79 CR[BA+id] <= compare(ireg[RA+ira], SI);
80 if (reg\_is\_vectorised[BA] ) \{ id += 1; \}
81 if (reg\_is\_vectorised[RA])  \{ ira += 1; \}
82 if test (CR[BA+id]) == FAIL: \{ VL = i + 1; break \}
83 \end{semiverbatim}
84
85 \begin{itemize}
86 \item Parallelism still perfectly possible
87 ("hold" writing results until sequential post-analysis
88 carried out. Best done with OoO)
89 \item VL truncation can be inclusive or exclusive
90 (include or exclude a NULL pointer or a
91 string-end character, or overflow result)
92 \item \textit{Truncation can be to zero Vector Length}
93 \end{itemize}
94 \end{frame}
95
96 \frame{\frametitle{Power ISA v3.1 vstribr}
97
98 \lstinputlisting[language={}]{vstribr.txt}
99
100 \begin{itemize}
101 \item ironically this hard-coded instruction is
102 identical to general-purpose Simple-V DD-FFirst...
103 \end{itemize}
104
105 }Po
106
107 \frame{\frametitle{maxloc}
108 \begin{itemize}
109 \item "TODO
110 \end{itemize}
111 }
112
113 \frame{\frametitle{Pospopcount}
114
115 \begin{itemize}
116 \item Positional popcount adds up the totals of each bit set to 1 in each bit-position, of an array of input values.
117 \item Notoriously difficult to do in SIMD assembler: typically 550 lines
118 \item https://github.com/clausecker/pospop
119
120 \end{itemize}
121
122 \lstinputlisting[language={}]{pospopcount.c}
123
124
125 }
126
127 \frame{\frametitle{Pospopcount}
128
129 \begin{center}
130 \includegraphics[width=0.5\textwidth]{pospopcount.png}
131 \end{center}
132 \begin{itemize}
133 \item The challenge is to perform an appropriate transpose of the data (the CPU can only work on registers, horizontally),
134 in blocks that suit the processor and the ISA capacity.
135
136
137 \end{itemize}
138 }
139
140 \frame{\frametitle{Pospopcount}
141
142 \begin{center}
143 \includegraphics[width=0.6\textwidth]{array_popcnt.png}
144 \end{center}
145
146 \begin{itemize}
147
148 \item The draft gbbd instruction implements the transpose (shown above),
149 preparing the data to use standard popcount.
150 (gbbd is based on Power ISA vgbbd, v3.1 p445)
151
152 \end{itemize}
153
154 }
155
156 \frame{\frametitle{Pospopcount.s}
157
158
159 \lstinputlisting[language={}]{pospopcount.s}
160
161 }
162
163
164 \frame{\frametitle{strncpy}
165
166 \lstinputlisting[language={}]{strncpy.c}
167 \begin{itemize}
168 \item "TODO
169 \end{itemize}
170 }
171
172
173
174 \frame{\frametitle{strncpy assembler}
175
176 \lstinputlisting[language={}]{strncpy.s}
177
178 }
179
180 \frame{\frametitle{sv.lbz/ff=RC1/vli *16,1(10)}
181 \begin{center}
182 \includegraphics[width=0.6\textwidth]{lbz_ff_vli.png}
183 \end{center}
184
185 \begin{itemize}
186 \item r10 points to memory address 0x001007
187 \item sv.lbz (Power ISA load byte immediate) multiplies immediate
188 offset by element step index, to get Effective Address (EA)
189 \item LD/ST has no Rc=1 so Data-Dependent Fail-First specified
190 as "ff=RC1". Not LD/ST Fault First! vli: VL inclusive
191 \item Test done after each load. Fails at Memory contents
192 0x001009. Inclusive Mode: VL is truncated to 5 (FIVE) not 4
193 \end{itemize}
194 }
195
196 \frame{\frametitle{linked-list walking}
197
198 \begin{itemize}
199 \item "TODO
200 \end{itemize}
201 }
202
203 \frame{\frametitle{sv.ld/ff=RC1/vli *17, 8(*16)}
204
205 \begin{center}
206 \includegraphics[width=1.0\textwidth]{linked_list_dd.png}
207 \end{center}
208 }
209
210 \frame{\frametitle{Summary}
211
212 \begin{itemize}
213 \item Goal is to create a mass-volume low-power embedded SoC suitable
214 for use in netbooks, chromebooks, tablets, smartphones, IoT SBCs.
215 \item No way we could implement a project of this magnitude without
216 nmigen (being able to use python OO to HDL)
217 \item Collaboration with OpenPOWER Foundation and Members absolutely
218 essential. No short-cuts. Standards to be developed and ratified
219 so that everyone benefits.
220 \item Riding the wave of huge stability of OpenPOWER ecosystem
221 \item Greatly simplified open 3D and Video drivers reduces product
222 development costs for customers
223 \item It also happens to be fascinating, deeply rewarding technically
224 challenging, and funded by NLnet
225
226 \end{itemize}
227 }
228
229 \frame{\frametitle{How can you help?}
230
231 \vspace{5pt}
232
233 \begin{itemize}
234 \item Start here! https://libre-soc.org \\
235 Mailing lists https://lists.libre-soc.org \\
236 IRC Freenode libre-soc \\
237 etc. etc. (it's a Libre project, go figure) \\
238 \vspace{3pt}
239 \item Can I get paid? Yes! NLnet funded\\
240 See https://libre-soc.org/nlnet/\#faq \\
241 \vspace{3pt}
242 \item Also profit-sharing in any commercial ventures \\
243 \vspace{3pt}
244 \item How many opportunities to develop Libre SoCs exist,\\
245 and actually get paid for it?
246 \vspace{3pt}
247 \item I'm not a developer, how can I help?\\
248 - Plenty of research needed, artwork, website \\
249 - Help find customers and OEMs willing to commit (LOI)
250 \end{itemize}
251 }
252
253
254
255 \frame{
256 \begin{center}
257 {\Huge The end\vspace{12pt}\\
258 Thank you\vspace{12pt}\\
259 Questions?\vspace{12pt}
260 }
261 \end{center}
262
263 \begin{itemize}
264 \item Discussion: http://lists.libre-soc.org
265 \item Freenode IRC \#libre-soc
266 \item http://libre-soc.org/
267 \item http://nlnet.nl/PET
268 \item https://libre-soc.org/nlnet/\#faq
269 \end{itemize}
270 }
271
272
273 \end{document}