conferences/fosdem2024/fosdem2024_tplaten/fosdem2024_tplaten.tex

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   7
   8 \title{Using the ECP5 for Libre-SOC prototyping}
   9 \author{Tobias Platen}
  10
  11
  12 \begin{document}
  13
  14 \frame{
  15   \begin{center}
  16     \huge{Using the ECP5 for Libre-SOC prototyping}\\
  17     \vspace{32pt}
  18     \Large{Verification of the Libre-SOC core}\\
  19     \Large{using an OrangeCrab feather form factor dev board}\\
  20     \Large{and gram to drive the ddr3 ram and booting Linux}\\
  21     \vspace{24pt}
  22     \Large{FOSDEM2024}\\
  23     \vspace{16pt}
  24     \large{Sponsored by NLnet}\\
  25     \vspace{6pt}
  26     \large{\today}
  27   \end{center}
  28 }
  29
  30
  31 \frame{\frametitle{Why using an ECP5 and OrangeCrab?}
  32
  33  \begin{itemize}
  34    \item ECP5 and ICE40 have libre toolchains (Yosys, nextpnr)\vspace{6pt}
  35    \item Microwatt already supports the OrangeCrab using LiteDRAM: \\
  36          LiteDRAM depens on original Migen and does not fit into ls2\\
  37          I was unable to rebuild the original one from Microwatt\\
  38          and decided to continue working on (nMigen based) gram
  39          \vspace{6pt}
  40    \item ECP5 is big enough for prototyping the Libre-SOC core\\
  41          When I started porting ls2 to the OrangeCrab I was able to\\
  42          run coldboot.c and began adding support for gram
  43    \vspace{6pt}
  44    \item Because for 5 years I Always Wanted To Design A GPU
  45    \vspace{6pt}
  46    \item ICE40 also used by Valve and Bitcraze in several SteamVR
  47          products and the Lighthouse positioning deck
  48   \end{itemize}
  49 }
  50
  51
  52 \frame{\frametitle{Why nMigen and gram?}
  53
  54 \vspace{15pt}
  55
  56  \begin{itemize}
  57    \item nMigen+LambdaSoC port of the LiteDRAM core\\
  58    avoiding using old Migen and LiteX\\
  59    only using nMigen used by Libre-SOC\vspace{10pt}
  60    \item nMigen is much more powerful than Verilog and VHDL\\
  61    and easier to use for anyone that knows python\\
  62    (and works with yosys/nextpnr/gcc)\vspace{10pt}
  63    \item gram is simplified, it only supports ECP5 atm\\
  64    and maybe some Xilinx FPGAs in the future \vspace{10pt}
  65    \item Wanting to learn how to use the dram phy that comes\\
  66    with the ECP5. Then booting linux using the Libre-SOC core
  67    \end{itemize}
  68 }
  69
  70
  71
  72
  73
  74 \frame{\frametitle{How do DRAM interfaces work}
  75 \vspace{9pt}
  76  \begin{itemize}
  77    \item Multiple generarions of DDR-SDRAM interfaces\\
  78          POWER9: DDR4-SDRAM  POWER10: DDR5-SDRAM
  79    \vspace{3pt}
  80    \item OrangeCrab has DDR3L Memory, 128 Mbytes (1Gbit)\\
  81          64M x16, 1.35V low voltage operation (can boot linux)
  82          \vspace{3pt}
  83    \item See nmigen-boards for OrangeCrab pins \vspace{3pt}
  84    \item Controller are found in gram and lite-dram\vspace{3pt}
  85    \item Ideally gram and lite-dram should show identical behaviour\\
  86          Reality: only lite-dram works out of the box
  87          \vspace{3pt}
  88    \item If it does not work debugging is hard\\
  89          Found out that burstdet signal is not asserted on read
  90   \end{itemize}
  91 }
  92
  93 \frame{\frametitle{The ECP5 DRAM controller}
  94
  95  \begin{itemize}
  96    \item see manual for ECP5 and ECP5-5G High-Speed I/O Interface\\
  97          comes with many built-in blocks: DQSBUFM, DDRDLLA, ...\\
  98          \textit{DQSBUFM} is the most interesting one\\
  99    \vspace{6pt}
 100    \item FPGA-TN-02035-1.3 documents DQSBUF \\
 101          Data Strobe Control Block : Generates a BURSTDET output\\
 102          that can be used to validate the READ pulse positioning\\
 103    \vspace{6pt}
 104    \item DQSBUFM element is used for all the DDR Memory\\
 105          interfaces on ECP5 only. Other blocks used on Xilinx
 106    \vspace{6pt}
 107    \item Python implementation of DDR PHY for ECP5\\
 108          git.libre-soc.org / gram.git / gram / phy / ecp5ddrphy.py\\
 109          github.com / enjoy-digital / litedram / phy / ecp5ddrphy.py
 110   \vspace{6pt}
 111   \end{itemize}
 112 }
 113
 114
 115
 116 \frame{\frametitle{Typical DDR2/DDR3/DDR3L Memory Interface}
 117   \begin{center}
 118     \includegraphics[width=0.9\textwidth]{interface1.png}
 119   \end{center}
 120 }
 121
 122 \frame{\frametitle{DQSBUFM -- Inputs}
 123   \begin{center}
 124     \includegraphics[width=0.9\textwidth]{DQSBUFM_P1.png}
 125   \end{center}
 126   \begin{itemize}
 127     \vspace{3pt}
 128     \item BURSTDET used for read leveling
 129     \item DATAVALID controls dfi.phases[0] and dfi.phases[1] latch
 130   \end{itemize}
 131 }
 132
 133 \frame{\frametitle{DQSBUFM -- Outputs}
 134   \begin{center}
 135     \includegraphics[width=0.9\textwidth]{DQSBUFM_P2.png}
 136   \end{center}
 137   \begin{itemize}
 138     \vspace{3pt}
 139       \item PAUSE controlled by init.pause and dqsbufm\_manager.pause
 140       \item READCLKSEL used to set read leveling delay (3 bits)
 141     \end{itemize}
 142 }
 143
 144 \frame{\frametitle{How to use libgram}
 145   \begin{itemize}
 146     \item struct gramCtx with base addresses and user data
 147     \item must call gram\_init(ctx, profile, ddr\_base, core\_base, phy\_base)
 148     \vspace{6pt}
 149      \item first phy is set to software control
 150      \item init seq is peformed
 151      \item then calibration is loaded
 152      \item phy is set to hardware control back again
 153      \vspace{6pt}
 154      \item finally memtest must run, we can boot linux if passed
 155      \vspace{6pt}
 156      \item calibration is different from litedram
 157   \end{itemize}
 158 }
 159
 160 \frame{\frametitle{Read leveling in litedram}
 161   \begin{itemize}
 162     \item only read leveling used by ECP5
 163     \item leveling must be done for each phy module
 164     \vspace{6pt}
 165      \item inner loop for bitslip
 166      \item A test each read window (bitslip)
 167      \item B find min/max delays
 168      \item take bitslip with best score
 169      \vspace{6pt}
 170      \item Re-do leveling on best read window
 171      \vspace{6pt}
 172      \item Sync all DQSBUFM's before scan(A) / level(B)
 173      \item Live demo using Microwatt
 174   \end{itemize}
 175 }
 176
 177 \frame{\frametitle{Write/readback test under software control}
 178   \begin{itemize}
 179   \item Generate pseudo-random sequence
 180   \item Activate test row
 181   \item Write pseudo-random sequence
 182   \vspace{6pt}
 183   \item ECP5: reset burstdet for current module
 184   \item Read/Check pseudo-random sequence
 185   \item Precharge
 186   \vspace{6pt}
 187   \item Read back test pattern
 188   \item Verify bytes matching current module
 189   \item ECP5: check burstdet for current module
 190   \vspace{9pt}
 191   \item DQSBUFM's not synced if burstdet is 0
 192   \item not yet implemented in gram
 193   \end{itemize}
 194 }
 195
 196 \frame{\frametitle{Debugging with BeagleWire}
 197 \begin{itemize}
 198 \item Fully Open iCE40 FPGA BeagleBone Cape
 199 \item 32 MB SDRAM and controller written in Verilog
 200 \item GPMC port access from the BeagleBone
 201 \vspace{6pt}
 202 \item no port to nMigen yet, toolchain on BBB
 203 \item connect to ECP5 to exchange data with host PC
 204 \item use SPI or I2CSlave for debugging
 205 \vspace{6pt}
 206 \item use iCE40/BBB as ROM emulator
 207 \item intercept read/write to SDRAM
 208 \item run gdbserver on BeagleBoneBlack
 209 \vspace{9pt}
 210 \item Long term: make EOMA68 card with Solid Silicon X1
 211 \item Two FPGAs and 512MB of DDR3 RAM
 212 \end{itemize}
 213 }
 214
 215 \frame{\frametitle{Porting nMigen to BeagleWire}
 216 \begin{itemize}
 217 \item There is only a LiteX port ATM
 218 \item Toolchain (yosys/arachne-pnr) running on BeagleBone
 219 \item Use python to control cross compile
 220 \vspace{6pt}
 221 \item run yosys on host PC, replace arachne-pnr
 222 \item generate bitstring for multiple FPGAs if needed
 223 \item control flashing via ssh, upload bitstring via scp
 224 \vspace{6pt}
 225 \item Unrelated to Libre-SOC: plans to make Lighthouse PMOD
 226 \item LibrePlanet 2022: The LibreVR Project
 227 \item http://librevr.isengaara.de
 228 \vspace{9pt}
 229 \item VR Headset will depend on Libre-SOC GPU
 230 \item run DOOM on iCE40/ECP5 FPGA -\> VGA output needed
 231 \end{itemize}
 232 }
 233
 234 \frame{\frametitle{Summary}
 235
 236  \begin{itemize}
 237    \item Microwatt can boot linux+buildroot on the OrangeCrab using LiteDRAM.
 238          Libre-SOC using ls2 needs more work on gram, including porting to
 239          other FPGAs.
 240    \item High speed interfaces differ between FPGA models and vendors and are hard to debug
 241          without using a simulator.
 242    \item Software gets more complex for larger designs, development becomes
 243          more expensive. Changes easily break everything.
 244    \item Once DRAM is working we can add other interfaces.
 245    \item Larger FPGA may be needed to prototype advanced features including
 246          GPU und display controller
 247    \item We can use the BeagleWire as a host computer interface
 248   \end{itemize}
 249 }
 250
 251
 252 \frame{
 253   \begin{center}
 254     {\Huge The end\vspace{12pt}\\
 255       Thank you\vspace{12pt}\\
 256    Questions?\vspace{12pt}
 257 }
 258   \end{center}
 259
 260   \begin{itemize}
 261   \item Discussion: http://lists.libre-soc.org
 262   \item Freenode IRC \#libre-soc
 263   \item http://libre-soc.org/
 264   \item http://nlnet.nl/PET
 265   \item https://libre-soc.org/nlnet/\#faq
 266   \end{itemize}
 267 }
 268
 269
 270 \end{document}