crypto_router_asic.mdwn

   1 # Crypto-router ASIC
   2
   3 <img src="https://www.ngi.eu/wp-content/uploads/sites/48/2020/04/Logo_Pointer.png" width="200px" />
   4 <img src="https://ngi.eu/wp-content/uploads/sites/77/2017/10/bandiera_stelle.png" width="50px" /><span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span>
   5 <img src="https://nlnet.nl/image/logos/NGIAssure_tag.svg" width="130px" />
   6 <span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span>
   7 <img src="https://www.artandtechnology.nl/logo.jpg" width="130px" />
   8
   9 **This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-POINTER Project funded under grant agreement No 871528**
  10
  11 **This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-ASSURE Project funded under grant agreement No 957073.**
  12
  13 * NLnet page: [[nlnet_2021_crypto_router]]
  14 * Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
  15 * ASIC/IO Pin specification page: [[crypto_router_asic/crypto_router_pinspec]]
  16
  17 # Specifications
  18
  19 All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
  20
  21 * 300 mhz single-core,
  22   [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD)
  23   OpenPOWER CPU with
  24   [[openpower/sv/bitmanip]] extensions
  25 * 180/130 nm (TBD)
  26 * 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs with
  27   [SRAM](https://github.com/adamgreig/daqnet/blob/master/gateware/daqnet/ethernet/rmii.py)
  28    on-chip, built-in.
  29 * 2x USB [[shakti/m_class/ULPI]] PHYs
  30 * Direct DMA interface (independent bulk transfer)
  31 * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
  32   GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
  33 * On-board Dual-ported SRAM (for Packet Buffers)
  34 * Opencores [[shakti/m_class/sdram]]
  35 * Wishbone interfaces to all peripherals
  36 * [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
  37   Interrupt Controller
  38
  39
  40
  41 # Example packet transfer
  42
  43 * Packet comes in on RGMII port 1.  Each PHY has its own dual-ported SRAM
  44 * Packet is **directly** stored in internal (dual-ported SRAM) by
  45   the RGMII PHY itself
  46 * Interrupt notification is sent to the processor (XICS)
  47 * Processor inspects packet over Wishbone interface directly
  48   connected to 2nd SRAM port.
  49 * Processor computes, based on decoding the ETH Frame, where the
  50   packet must be sent to (which other RGM-II port: e.g. Port 2)
  51 * Processor initiates Memory-to-Memory DMA transfer
  52 * DMA Memory-to-Memory transfer, using Wishbone Bus, copies the ETH Frame
  53   from one on-board SRAM to the target on-board SRAM associated with Port 2.
  54 * DMA Engine generates interrupt (XICS) to the CPU to say it is completed
  55 * Processor notifies target RGM-II PHY to activate "send" of frame out
  56   through target RGM-II port 2.
  57
  58 # Testing and Verification
  59
  60 We will need full HDL simulations as well as post P&R simulations.
  61 These may be achieved as follows:
  62
  63 * ISA-level unit tests as well as Formal Correctness Proofs.
  64   Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
  65   and individual unit tests for the
  66   [Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
  67 * simulation
  68   with some peripherals developed in c++ as verilator modules
  69 * nmigen-based OpenPOWER Libre-SOC core co-simulation such as
  70   this unit test,
  71   [test_issuer.py](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_issuer.py;hb=HEAD)
  72 * [cocotb pre/post PnR](https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=tree;f=ls180;hb=HEAD) including GHDL, Icarus and Verilator
  73   (where best suited)
  74
  75 Actual instructions being developed (bitmanip) may therefore be
  76 unit tested prior to deployment.  Following that, rapid simulations
  77 may be achieved by running Litex (the same HDL may also easily
  78 be uploaded to an FPGA).  When it comes to Place-and-Route of the
  79 ASIC, the cocotb simulations may be used to verify that the GDS-II
  80 layout has not been "damaged" by the PnR tools.
  81
  82 Peripherals functionality tests must also be part of the simulations,
  83 particularly using cocotb, to ensure that they remain functional after PnR.
  84 Supercomputer access for compilation of verilator and/or cxxrtl is available
  85 through [[fed4fire]]
  86