interrupts/interrupt_handling.mdwn

   1 # Interrupt Handling in RISC-V
   2
   3 This is a non-authoritative document for informally capturing the
   4 requirements for interrupt handling across the spectrum of the entire
   5 RISC-V ecosystem, with a view to finding common ground.  Following on
   6 from that will be seeing where collaboration is (and is not) feasible,
   7 and, crucially, if the existing structures (such as the various PLIC
   8 implementations that already exist) cover peoples' needs (or not).
   9
  10 # Requirements Discussion
  11
  12 This section is intended for capturing requirements from different sources
  13 so that they can be viewed and compared in one place.  If you are not
  14 familiar with markdown or editing of wikis please contact
  15 luke.leighton@gmail.com, sending the appropriate text, for inclusion here.
  16
  17 * **Libre-RISCV Shakti M-Class**: a 300-400 pin SoC with almost a hundred
  18   separate and distinct "slow" (below 160mhz) peripherals that need
  19   nothing particularly special in the way of fast latency IRQs, just lots
  20   of them.  Five UARTs, each requiring one IRQ line; Four I2C peripherals,
  21   each requiring two IRQ lines, Multiple Quad SPI interfaces requring
  22   **six** IRQ lines (each!), and 32 "EINT" lines (general-purpose
  23   external interrupt) which are intended for mundane purposes such as
  24   "lid opened", or "volume key pressed" and "headphone jack inserted",
  25   the number of IRQ lines required to cover such a significant number
  26   of peripherals begins to add up quite rapidly.  However despite this,
  27   the PLIC as it stands (privspec-v-1.10 chapter 7) actually covers the
  28   requirements quite nicely, as long as it can cope with large numbers
  29   *of* IRQ lines (which it can).  Thus the Shakti PLIC Peripheral code
  30   has been modified from its original (which could handle up to XLEN
  31   separate lines) to a hierarchical arrangement that can handle up to
  32   1024 separate and distinct IRQs
  33   <http://git.libre-riscv.org/?p=shakti-peripherals.git;a=blob;f=src/peripherals/plic/plic.bsv>.  A code-generator tool
  34   <http://git.libre-riscv.org/?p=pinmux.git> will take care of the task
  35   of auto-generating the #defines for the linux kernel, and presently
  36   already takes care of the task of generating the PLIC fabric interconnect.
  37
  38