ipc_extension.mdwn

   1 # IPC Extension
   2
   3 see Tony Brewer's (Micron) slides.
   4
   5 idea: copy POSIX send/recv/select semantics
   6
   7 dependency(?): scratch/CAM memory extension
   8
   9 * MSTORE: message send; send message to a target hart) and store it in
  10   its message-buffer. Traps when target buffer is full.
  11 * MLOAD: message load; load message from local message buffer. Traps
  12   when buffer is empty.
  13 * MFLUSH(?): flush local buffer
  14 * MSELECT: check if send (or receive) can succeed (or block)
  15
  16 MSEND can be like ST, but I chose to have a return value to indicate
  17 whether the send was accepted (i.e., copied into xmit buffer). this
  18 enables sharing of resources at the sender (future senders will be
  19 denied until the xmit buffer has space).
  20
  21 MRECV has two versions, blocking and non-blocking. the non-blocking
  22 version allows the hart to do a bit more work before checking whether
  23 data has arrived. the blocking version waits until data is received.
  24
  25 to improve upon the messaging system I described, there would need to
  26 be backing storage in main memory for the CAM data. perhaps the CAM
  27 needs to operate with an eviction policy based upon oldest-first. main
  28 memory would then store anything that is evicted. that way any values
  29 in the CAM that aren't used right away will migrate into main memory;
  30 it is acceptable to move them there because this is already a high
  31
  32 Maybe the *newest* message should spill to memory instead?  This keeps
  33 messages in FIFO order and could be easier to implement -- MSEND traps,
  34 supervisor transfers the message to memory and sets a bit in the target's
  35 task state indicating "RX queue overflow".  When the target task finally
  36 does drain its RX queue, and that bit is set, MRECV traps to permit the
  37 supervisor to reload the hardware queue from the memory overflow area.
  38
  39 This avoids needing background DMA for the message buffers in hardware
  40 and allows supervisors to fully implement the overflow queues, rather
  41 than forcing a hardware-imposed structure.