nlnet_2019_standards.mdwn

   1 # NL.net proposal - 2019-10-046
   2
   3 * NLNet Project Page <https://nlnet.nl/project/LibreSoC-Standards/>
   4 * Top Level bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=174>
   5
   6 ## Project name
   7
   8 The Libre RISC-V SoC, Formal Standards Development
   9
  10 ## Website / wiki
  11
  12 <https://libre-riscv.org/nlnet_2019_standards>
  13
  14 Please be short and to the point in your answers; focus primarily on
  15 the what and how, not so much on the why. Add longer descriptions as
  16 attachments (see below). If English isn't your first language, don't
  17 worry - our reviewers don't care about spelling errors, only about
  18 great ideas. We apologise for the inconvenience of having to submit in
  19 English. On the up side, you can be as technical as you need to be (but
  20 you don't have to). Do stay concrete. Use plain text in your reply only,
  21 if you need any HTML to make your point please include this as attachment.
  22
  23 ## Abstract: Can you explain the whole project and its expected outcome(s).
  24
  25 The Libre RISC-V SoC is a hybrid CPU, VPU and GPU which is being designed
  26 to be libre to the bedrock. When the hardware is transparently auditable,
  27 it can be trusted to not secretly compromise the software running on it.
  28
  29 With RISC-V being in its early infancy, however, Standards for Video
  30 Acceleration and 3D Graphics Acceleration do not yet exist.  These need
  31 to be written, proposed, formally ratified and Conformance Test Suites
  32 written and likewise ratified.
  33
  34 This takes a huge amount of time and coordinated collaboration, and is
  35 a necessary co-dependent task alongside the actual development of the
  36 processor itself.
  37
  38
  39 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  40
  41 Luke Leighton is an ethical technology specialist who has a consistent
  42 24-year track record of developing code in a real-time transparent
  43 (fully libre) fashion, and in managing Software Libre teams. He is the
  44 lead developer on the Libre RISC-V SoC.
  45
  46 # Requested Amount
  47
  48 EUR 50,000.
  49
  50 # Explain what the requested budget will be used for?
  51
  52 The improvements and additions to RISC-V Standards (known as Extensions)
  53 need to be written, reviewed thoroughly, justification for the features
  54 given, and then proposed.
  55
  56 There are several (see links at end) already in draft form. The primary
  57 one is the Vectorisation Standard. Additional Vector Operations is
  58 another. Transcendental operations (SIN, COS, LOG) another.
  59
  60 Once drafts have been agreed, a simulator can be developed. Next is some
  61 unit tests, and after that, some formal Compliance Tests.
  62
  63 Finally this can be submitted to the RISC-V Foundation for formal
  64 adoption.
  65
  66 Traveling expenses for presenting the standards to the RISC-V community
  67 at Libre Conferences as well as RISC-V Workshops are needed.
  68
  69 Writing up of papers on the core technology and discoveries behind the
  70 standards, for presentation at IEEE and other Computing Conferences.
  71 This to aid in understanding of the need for the Standards and to
  72 make adoption easier.
  73
  74 # Does the project have other funding sources, both past and present?
  75
  76 The initial proposal in November 2018 was for implementation of the
  77 actual processor, as well as writing a simulator and developing Kazan,
  78 the 3D Vulkan Driver. Purism began also sponsoring the overall project
  79 in mid 2019.
  80
  81 It was discovered only in September 2019 on an offchance comment from
  82 someone inside the (closed participation) RISC-V Foundation that RISC-V
  83 Standards require a full Conformance Compliance Test Suite as part
  84 of formal acceptance.  This easily doubles the workload of Standards
  85 Development and is in no way coverable by the initial 2018 proposal.
  86
  87 # Compare your own project with existing or historical efforts.
  88
  89 RISC-V is in its early infancy and has neither Extensions for 3D nor
  90 Video.  Most off the shelf commercial SoCs will use a special custom block
  91 for Video, and a separate GPU for 3D. Each of these, bring proprietary,
  92 is an attack vector for privacy subversion.
  93
  94 In this project, the CPU *is* the VPU and the GPU, so there is nothing to
  95 compare it against.  The full transparency of the Standards Development
  96 Process is a necessary prerequisite for being able to trust the end
  97 result.
  98
  99 ## What are significant technical challenges you expect to solve during the project, if any?
 100
 101 The key challenge will not be technical, it is a communications issue. The
 102 RISC-V Foundation operates as a closed ITU Style Standards Organisation,
 103 requiring effectively an NDA for participation, with negligeable
 104 transparency and zero accountability.
 105
 106 A two year protracted and persistent request for open participation
 107 and recognition of the value of the same is finally starting to get
 108 action taken.
 109
 110 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes
 111
 112 As mentioned in the 2018 submission, the Libre RISC-V
 113 SoC has a full set of resources for Libre Project Management and development:
 114 mailing list, bugtracker, git repository and wiki - all listed here:
 115 <https://libre-riscv.org/>
 116
 117 In addition, we have a Crowdsupply page
 118 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 119 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 120 all picked up the story.  The list is updated and maintained here:
 121 <https://libre-riscv.org/3d_gpu/>
 122
 123 # Extra info to be submitted
 124
 125 * <http://libre-riscv.org/3d_gpu/>
 126 * <https://nlnet.nl/project/Libre-RISCV/>
 127 * <https://libre-riscv.org/simple_v_extension/>
 128 * <https://libre-riscv.org/ztrans_proposal/>
 129 * <https://libre-riscv.org/zfpacc_proposal/>
 130 * Several other sub-proposals as part of the above.
 131
 132 # Management Summary
 133
 134 The Libre SoC was first funded from NLNet in 2018.  This was for the core
 135 of the project, based on an informally-developed Hybrid CPU-GPU 3D
 136 instruction set that had been written (and implemented in a simulator)
 137 in the 18 months prior to contacting NLNet.  During the implementation
 138 it became clear that a lot more work would be needed, and, further, that
 139 to meet proper transparency criteria, the proposed instruction set
 140 enhancements would need to be properly written up.  In addition,
 141 negotiations and communications with the Standards Body responsible
 142 for POWER ISA (the OpenPower Foundation) also needed to be taken into
 143 consideration.  Therefore this proposal was submitted so that full
 144 transparency and understanding of the Libre SoC is achieved.