nlnet_2022_ongoing.mdwn

   1 # NL.net proposal
   2
   3 **This project is part of [NLnet NGI0 Entrust](https://nlnet.nl/entrust)
   4 and has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No 101069594.**
   5
   6 * 2022-08E-107
   7 * [[nlnet_2022_ongoing/discussion]]
   8 * <https://bugs.libre-soc.org/show_bug.cgi?id=961>
   9
  10 ## Project name
  11
  12 Libre-SOC Ongoing 2022/3
  13
  14 ## Website / wiki
  15
  16 <https://libre-soc.org/nlnet_2022_ongoing>
  17
  18 # Summary
  19
  20 The funding to date from NLnet via EU Grants has been amazing and resulted
  21 in significant development of Digitally-Sovereign VLSI designs.
  22 Continuing to further that initial research to create High Performance
  23 Compute for ultimate use in end-user products such as smartphones desktops
  24 laptops and Industrial Embedded PCs is clearly important.
  25 We therefore aim to further the IEEE754 Pipelines, associated Formal
  26 Correctness Proofs, and continue implementing unit tests, Simulator,
  27 Processor Core implementing Power ISA and Draft SVP64, as well as
  28 documentation and attending conferences.
  29
  30 # Submitted to NLnet
  31
  32 Please be short and to the point in your answers; focus primarily on
  33 the what and how, not so much on the why. Add longer descriptions as
  34 attachments (see below). If English isn't your first language, don't
  35 worry - our reviewers don't care about spelling errors, only about
  36 great ideas. We apologise for the inconvenience of having to submit in
  37 English. On the up side, you can be as technical as you need to be (but
  38 you don't have to). Do stay concrete. Use plain text in your reply only,
  39 if you need any HTML to make your point please include this as attachment.
  40
  41 ## Abstract: Can you explain the whole project and its expected outcome(s).
  42
  43 Libre-SOC aims to create a Supercomputing-class entirely Libre Hybrid
  44 CPU-VPU-GPU. In proposal 2022-08-51 we aim to begin the long process
  45 of submitting the required Scalable Vector Extension to the OpenPOWER
  46 Foundation: this Grant Request focusses more on continuing to
  47 *implement* that Scalable Vector Extension.
  48
  49 With the entire project being 100% FOSSHW and managed strictly as a
  50 Libre Project under strict Full Transparency conditions the end result
  51 is a High-performance Processor Initiative that EU Citizens can trust.
  52
  53 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  54
  55 As mentioned in 2022-08-51,
  56 a lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  57 and includes
  58
  59 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  60 * the world's first in-place Discrete Cosine Transform algorithm;
  61 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
  62  to do an 800,000 transistor fully automated RTL2GDSII
  63 tape-out;
  64 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
  65   ASIC ever taped-out in Europe (and funded by Horizon 2020)
  66 * development of an Interoperability "Test API" for Power ISA systems,
  67   with thousands of unit tests.
  68
  69 and much more. The side-benefits alone for EU citizens are enormous.
  70
  71 # Requested Amount
  72
  73 EUR 100,000.
  74
  75 # Explain what the requested budget will be used for?
  76
  77 (Note having completed 2022-02-012 we meet the conditions for a
  78 larger budget request)
  79
  80 Whilst 2022-08-51 focusses on submitting SVP64 to the OpenPOWER ISA WG,
  81 and satisfying Voting Members of its suitability, we need to proceed
  82 with implementing SVP64 and underlying infrastructure:
  83
  84 * Dynamic Partitioned SIMD for nmigen
  85 * Completion of IEEE754 FP Formal Correctness Proofs
  86 * Completion of an In-Order Single-Issue core implementing SVP64
  87 * Addition of the IEEE754 FPU to the Core
  88 * Addition of other ALUs and pipelines (bitmanip, video)
  89   implementing new Draft instructions from 2022-08-051
  90 * Addition of SMP (multi-core) support
  91 * Running under Verilator and on FPGAs (big ones) which will
  92   need to be investigated, bought, and the Libre-Licensed tools support
  93   potentially added or improved
  94 * Continued documentation, attendance of Conferences online
  95 * Begin investigating Multi-Issue Out-of-Order, continuing
  96   the 6600 Scoreboard research from 2019-02-012
  97 * Establishment and management of Continuous Integration
  98   infrastructure and upgrading the Libre-SOC IT systems
  99   (currently a single 4GB VM)
 100 * If there is sufficient budget we would like to begin investigating
 101   OpenCAPI (we have access to two Bitmain 250 FPGAs thanks to UOregon)
 102
 103 several more practical details which help very much to ensure that the
 104 efforts to date, funded very kindly by NLnet, reach fruition as part
 105 of providing EU Citizens with a powerful Libre alternative processor
 106 option.
 107
 108 # Compare your own project with existing or historical efforts.
 109
 110 As hinted at in 2022-08-051
 111 we are basically developing a Cray-style Supercomputer, leveraging
 112 the Supercomputing-class Power ISA
 113 and extending it.  Similar historic ISAs include
 114 Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
 115 They are all proprietary systems: Libre-SOC's efforts are entirely
 116 FOSSHW.
 117
 118 Whilst the European Processor Initiative is focussing exclusively
 119 on RISC-V, due to the amount of time it takes to assess an ISA's
 120 suitability it has to be said that it is being discovered, very slowly,
 121 that RISC-V is not suited to High-Performance Supercomputing
 122 workloads. The best explanation online is here:
 123 <https://news.ycombinator.com/item?id=24459041>
 124
 125 Therefore this project is a really important alternative
 126 being based on a much more suitable High-performance
 127 base that has the backing of
 128 IBM for over 25 years, and is now an Open ISA.
 129 <https://openpowerfoundation.org/blog/final-draft-of-the-power-isa-eula-released/>
 130
 131 ## What are significant technical challenges you expect to solve during the project, if any?
 132
 133 Processor design is HARD. This is dramatically underestimated.  We are
 134 therefore taking a careful and considered incremental approach, using
 135 Software Engineering programming techniques, developing unit tests
 136 at every level and ensuring rigorous documentation and Project coordination
 137 guidelines are adhered to.
 138
 139 We also make significant use of automation,
 140 compiler technology and abstraction
 141 which would never be considered by Hardware-only VLSI Engineers.
 142 By taking a step back we simplify the approach to one that is
 143 manageable by a much smaller team.
 144
 145 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 146
 147 As in 2022-08-051
 148 we are already set to submit presentations through multiple Conferences
 149 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 150 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 151 so is accessible to all.
 152
 153 # Extra info to be submitted
 154