nlnet_2022_ongoing.mdwn

   1 # NL.net proposal
   2
   3 * 2022-08-107
   4 * [[nlnet_2022_ongoing/discussion]]
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=961>
   6
   7 ## Project name
   8
   9 Libre-SOC Ongoing 2022/3
  10
  11 ## Website / wiki
  12
  13 <https://libre-soc.org/nlnet_2022_ongoing>
  14
  15 # Summary
  16
  17 The funding to date from NLnet via EU Grants has been amazing and resulted
  18 in significant development of Digitally-Sovereign VLSI designs.
  19 Continuing to further that initial research to create High Performance
  20 Compute for ultimate use in end-user products such as smartphones desktops
  21 laptops and Industrial Embedded PCs is clearly important.
  22 We therefore aim to further the IEEE754 Pipelines, associated Formal
  23 Correctness Proofs, and continue implementing unit tests, Simulator,
  24 Processor Core implementing Power ISA and Draft SVP64, as well as
  25 documentation and attending conferences.
  26
  27 # Submitted to NLnet
  28
  29 Please be short and to the point in your answers; focus primarily on
  30 the what and how, not so much on the why. Add longer descriptions as
  31 attachments (see below). If English isn't your first language, don't
  32 worry - our reviewers don't care about spelling errors, only about
  33 great ideas. We apologise for the inconvenience of having to submit in
  34 English. On the up side, you can be as technical as you need to be (but
  35 you don't have to). Do stay concrete. Use plain text in your reply only,
  36 if you need any HTML to make your point please include this as attachment.
  37
  38 ## Abstract: Can you explain the whole project and its expected outcome(s).
  39
  40 Libre-SOC aims to create a Supercomputing-class entirely Libre Hybrid
  41 CPU-VPU-GPU. In proposal 2022-08-51 we aim to begin the long process
  42 of submitting the required Scalable Vector Extension to the OpenPOWER
  43 Foundation: this Grant Request focusses more on continuing to
  44 *implement* that Scalable Vector Extension.
  45
  46 With the entire project being 100% FOSSHW and managed strictly as a
  47 Libre Project under strict Full Transparency conditions the end result
  48 is a High-performance Processor Initiative that EU Citizens can trust.
  49
  50 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  51
  52 As mentioned in 2022-08-51,
  53 a lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  54 and includes
  55
  56 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  57 * the world's first in-place Discrete Cosine Transform algorithm;
  58 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
  59  to do an 800,000 transistor fully automated RTL2GDSII
  60 tape-out;
  61 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
  62   ASIC ever taped-out in Europe (and funded by Horizon 2020)
  63 * development of an Interoperability "Test API" for Power ISA systems,
  64   with thousands of unit tests.
  65
  66 and much more. The side-benefits alone for EU citizens are enormous.
  67
  68 # Requested Amount
  69
  70 EUR 100,000.
  71
  72 # Explain what the requested budget will be used for?
  73
  74 (Note having completed 2022-02-012 we meet the conditions for a
  75 larger budget request)
  76
  77 Whilst 2022-08-51 focusses on submitting SVP64 to the OpenPOWER ISA WG,
  78 and satisfying Voting Members of its suitability, we need to proceed
  79 with implementing SVP64 and underlying infrastructure:
  80
  81 * Dynamic Partitioned SIMD for nmigen
  82 * Completion of IEEE754 FP Formal Correctness Proofs
  83 * Completion of an In-Order Single-Issue core implementing SVP64
  84 * Addition of the IEEE754 FPU to the Core
  85 * Addition of other ALUs and pipelines (bitmanip, video)
  86   implementing new Draft instructions from 2022-08-051
  87 * Addition of SMP (multi-core) support
  88 * Running under Verilator and on FPGAs (big ones) which will
  89   need to be investigated, bought, and the Libre-Licensed tools support
  90   potentially added or improved
  91 * Continued documentation, attendance of Conferences online
  92 * Begin investigating Multi-Issue Out-of-Order, continuing
  93   the 6600 Scoreboard research from 2019-02-012
  94 * Establishment and management of Continuous Integration
  95   infrastructure and upgrading the Libre-SOC IT systems
  96   (currently a single 4GB VM)
  97 * If there is sufficient budget we would like to begin investigating
  98   OpenCAPI (we have access to two Bitmain 250 FPGAs thanks to UOregon)
  99
 100 several more practical details which help very much to ensure that the
 101 efforts to date, funded very kindly by NLnet, reach fruition as part
 102 of providing EU Citizens with a powerful Libre alternative processor
 103 option.
 104
 105 # Compare your own project with existing or historical efforts.
 106
 107 As hinted at in 2022-08-051
 108 we are basically developing a Cray-style Supercomputer, leveraging
 109 the Supercomputing-class Power ISA
 110 and extending it.  Similar historic ISAs include
 111 Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
 112 They are all proprietary systems: Libre-SOC's efforts are entirely
 113 FOSSHW.
 114
 115 Whilst the European Processor Initiative is focussing exclusively
 116 on RISC-V, due to the amount of time it takes to assess an ISA's
 117 suitability it has to be said that it is being discovered, very slowly,
 118 that RISC-V is not suited to High-Performance Supercomputing
 119 workloads. The best explanation online is here:
 120 <https://news.ycombinator.com/item?id=24459041>
 121
 122 Therefore this project is a really important alternative
 123 being based on a much more suitable High-performance
 124 base that has the backing of
 125 IBM for over 25 years, and is now an Open ISA.
 126 <https://openpowerfoundation.org/blog/final-draft-of-the-power-isa-eula-released/>
 127
 128 ## What are significant technical challenges you expect to solve during the project, if any?
 129
 130 Processor design is HARD. This is dramatically underestimated.  We are
 131 therefore taking a careful and considered incremental approach, using
 132 Software Engineering programming techniques, developing unit tests
 133 at every level and ensuring rigorous documentation and Project coordination
 134 guidelines are adhered to.
 135
 136 We also make significant use of automation,
 137 compiler technology and abstraction
 138 which would never be considered by Hardware-only VLSI Engineers.
 139 By taking a step back we simplify the approach to one that is
 140 manageable by a much smaller team.
 141
 142 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 143
 144 As in 2022-08-051
 145 we are already set to submit presentations through multiple Conferences
 146 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 147 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 148 so is accessible to all.
 149
 150 # Extra info to be submitted
 151