nlnet_2022_opf_isa_wg.mdwn

   1 # NL.net proposal
   2
   3 * 2022-08-051, approved 24 Oct 2022
   4 * [[nlnet_2022_opf_isa_wg/discussion]]
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=952>
   6
   7 ## Project name
   8
   9 Libre-SOC OpenPOWER ISA RFCs
  10
  11 ## Website / wiki
  12
  13 <https://libre-soc.org/nlnet_2022_opf_isa_wg>
  14
  15 ## NLnet Funding approved 25-Oct-2022 under EU Grant 101069594
  16
  17 This project is funded through the [NGI Zero Entrust Fund](https://nlnet.nl/entrust), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) program. Learn more on the [NLnet project page](https://nlnet.nl/project/Libre-SOC-OpenPOWER-ISA#ack).
  18
  19
  20 [<img src="https://nlnet.nl/logo/banner.png" alt="NLnet foundation logo" width="20%" />](https://nlnet.nl)
  21 [<img src="https://nlnet.nl/image/logos/NGI0Entrust_tag.svg" alt="NGI Zero Entrust Logo" width="20%" />](https://nlnet.nl/entrust)
  22
  23 # Summary
  24
  25 In earlier NLnet Grants, thanks to EU funding, we developed Draft
  26 SVP64 (a Vector Extension for the Power ISA), around a hundred
  27 new Draft instructions that dramatically improves the Supercomputing-class
  28 Power ISA, a Simulator, thousands
  29 of unit tests and over 350 pages of documentation.  What we could
  30 not do however was submit a Specification to the OpenPOWER ISA
  31 Working Group because the ISA WG was in the process of being
  32 ratified.  That has now been done, and we need to begin the
  33 formal process of writing up "Requests For Change" and submitting
  34 them. The end result will be an extremely powerful Vector ISA suitable
  35 for use in Digitally-Sovereign end-user products.
  36
  37 # Submission to NLnet
  38
  39 Please be short and to the point in your answers; focus primarily on
  40 the what and how, not so much on the why. Add longer descriptions as
  41 attachments (see below). If English isn't your first language, don't
  42 worry - our reviewers don't care about spelling errors, only about
  43 great ideas. We apologise for the inconvenience of having to submit in
  44 English. On the up side, you can be as technical as you need to be (but
  45 you don't have to). Do stay concrete. Use plain text in your reply only,
  46 if you need any HTML to make your point please include this as attachment.
  47
  48 ## Abstract: Can you explain the whole project and its expected outcome(s).
  49
  50 The current NLnet funding to date has allowed Libre-SOC to develop
  51 one of the most powerful Scalable Vector ISAs in the world.
  52 The 25-year-old Power ISA, developed and curated by IBM, was
  53 transferred to the OpenPOWER Foundation, and is the basis on
  54 which, with NLnet EU funding, we have based
  55 Simple-V, the Draft Scalable Vector Extension.
  56
  57 Simple-V *needs* to be submitted to the OPF ISA Working Group,
  58 for formal discussion and inclusion. Given that it is 380
  59 pages we expect this to be done carefully and incrementally.
  60 https://ftp.libre-soc.org/simple_v_spec.pdf
  61
  62 However the
  63 process of submitting RFCs (Requests For Change), at the time of writing,
  64 still has not been publicly announced and opened up. We expect it
  65 to be very soon, but obviously could not begin any RFC Submission
  66 as part of earlier NLnet funding.  The timing is now right.
  67
  68 We will become publicly informed very shortly of the procedures but anticipate
  69 it to include development and submission of Compliance Test Suites
  70 (already partly covered by Simple-V unit tests, kindly funded by NLnet)
  71 as well as ongoing work on the Simulator.
  72
  73 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  74
  75 A lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  76 and includes
  77
  78 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  79 * the world's first in-place Discrete Cosine Transform algorithm;
  80 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
  81  to do an 800,000 transistor fully automated RTL2GDSII
  82 tape-out;
  83 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
  84   ASIC ever taped-out in Europe (and funded by Horizon 2020)
  85 * development of an Interoperability "Test API" for Power ISA systems,
  86   with thousands of unit tests.
  87
  88 and much more. The side-benefits alone for EU citizens are enormous.
  89
  90 # Requested Amount
  91
  92 EUR 100,000.
  93
  94 # Explain what the requested budget will be used for?
  95
  96 Time and resource, primarily manpower, to prepare and submit the documentation
  97 to OPF. To give us legal compliance for the development
  98 work carried out over the past four years, as part of the
  99 transfer to the OpenPOWER Foundation.
 100
 101 * ongoing communication with the OpenPOWER Foundation ISA Working Group
 102 * preparation of a large number of RFCs (380 pages total so far) through
 103   the External RFC Process
 104 * for each RFC accepted, work needs to be done with IBM to submit Power ISA Spec
 105   changes
 106 * for each RFC accepted, a Compliance Test Suite must be written
 107 * for each Compliance Test Suite written the results must be
 108   confirmed correct by inspection (hence the Simulator) which has
 109   as we already discovered been quite a lot of work
 110 * Along the way we aim to continue developing the "Test API" which
 111   allows running thousands of unit tests on multiple systems and
 112   cross-checking the results.  Currently we have Simulator, some
 113   "Expected Results", and the Libre-SOC HDL as well as qemu.
 114   We aim to add cavatools, gem5, Microwatt and stand-alone binary
 115   auto-generation for running on IBM POWER9 as well as Libre-SOC
 116   and Microwatt FPGAs.
 117
 118 # Compare your own project with existing or historical efforts.
 119
 120 We are developing a Cray-style Scalable Vector ISA Extension for
 121 the Supercomputing-class Power ISA.  Similar historic ISAs include
 122 Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
 123 They are all proprietary systems: Libre-SOC's efforts are entirely
 124 FOSSHW.
 125
 126 Open Scalable Vector ISAs include MRISC32/64 (in early development) and
 127 RISC-V RVV. Advocates of RISC-V have been discovering to their dismay
 128 that RVV and RISC-V ISA has fundamental design issues that cannot be fixed.
 129 Additionally, submission of RISCV ISA modifications requires RISCV Foundation
 130 Membership which puts us under impossible conflict of interest with
 131 Full Transparency Conditions not only with NLnet but also with
 132 EU Auditing Requirements.  By direct contrast OPF External RFC Submission
 133 does not require Secrecy.
 134
 135 ## What are significant technical challenges you expect to solve during the project, if any?
 136
 137 The main challenge is one of communication. The majority of the technical
 138 development has been done thanks to NLnet
 139 but it was so complex and comprehensive that it risks overwhelming the ISA
 140 WG Members, whose primary driver has of course been IBM for the past 25
 141 years.
 142
 143 Libre-SOC proposes taking the Power ISA into mainstream computing,
 144 including Video Decode, 3D, GPU workloads, cryptography, and Desktop
 145 and Portable devices, all of which are far different from IBM's traditional
 146 Mainframe-style multi-billion-dollar Supercomputing business.
 147 We therefore have to be both deeply respectful of their achievements, and
 148 non-disruptive to their customer base, but
 149 also appropriately assertive now that the ISA is managed by the OpenPOWER
 150 Foundation.
 151
 152 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 153
 154 Partly covered above, Libre-SOC is exclusively FOSSHW and full transparency
 155 is paramount. That said we recognise that no FOSSHW team is going to
 156 manufacture FOSS ASICs in 7nm (unless several billion dollars is available
 157 to buy a Foundry and open up its PDK). To that end RED Semiconductor Ltd
 158 has been formed by us as an Independent Entity,
 159 which will commercialise Libre-SOC's designs and handle
 160 any Commercially-confidential matters that a Transparency-committed
 161 FOSSHW team simply
 162 cannot. Thus, RS will join the OpenPOWER Foundation and help ensure,
 163 from the "other side of the fence", that matters progress smoothly
 164 for IBM and other OPF Members.
 165
 166 RED Semiconductor Ltd will the commercial point of contact for Simple-V
 167 where Organisations are unable to deal with FOSS Entities. This maximises
 168 the broad market benefit of the technology, in line with European Objectives.
 169
 170 We are already set to submit presentations through multiple Conferences
 171 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 172 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 173 so is accessible to all.
 174
 175 # Extra info to be submitted
 176
 177 the budget is high because we honestly do not know yet how much work
 178 IBM and the ISA WG expects us to do.  we do however know that there
 179 will be announcements very soon. If it turns out to be less work
 180 we are more than happy to go with a proportionately smaller budget.