openpower.mdwn

   1 # OpenPOWER
   2
   3 In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors.
   4 This evolved to a specification known as the POWER ISA. In 2019 IBM made the POWER ISA [[!wikipedia Open_source]], to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]]. These IBM proprietary processors
   5 happen to implement what is now known as the POWER ISA. The names
   6 POWER8, POWER9, POWER10 etc. are product designations equivalent to Intel
   7 i5, i7, i9 etc. and are frequently conflated with versions of the POWER ISA (v2.07, v3.0c, v3.1b).
   8
   9 Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on POWER ISA, because it wants to be able to specify a machine that can be completely trusted, and because POWER, thanks to IBM's involvement,
  10 is designed for high performance.
  11
  12 See wikipedia page
  13 <https://en.m.wikipedia.org/wiki/Power_ISA>
  14
  15 very useful resource describing all assembly instructions
  16 <https://www.ibm.com/docs/en/aix/7.1?topic=reference-instruction-set>
  17
  18 # Evaluation
  19
  20 EULA released! looks good.
  21 <https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/>
  22
  23 # Links
  24
  25 * OpenPOWER Membership
  26   <https://openpowerfoundation.org/join/>
  27 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
  28 * [[openpower/isatables]]
  29 * [[openpower/whitepapers]]
  30 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
  31 * [[openpower/gem5]]
  32 * [[openpower/sv]]
  33 * [[openpower/prefix_codes]] Decode/encode prefix-codes, used by JPEG, DEFLATE, etc.
  34 * [[openpower/opcode_regs_deduped]]
  35 * [[openpower/simd_vsx]]
  36 * [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
  37 * [[openpower/pearpc]]
  38 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
  39 * [[3d_gpu/architecture/decoder]]
  40 * <https://forums.raptorcs.com/>
  41 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  42 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  43 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  44 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  45 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  46
  47 PowerPC Unit Tests
  48
  49 * <https://github.com/lioncash/DolphinPPCTests>
  50 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  51
  52 Summary
  53
  54 * FP32 is converted to FP64. Requires SimpleV to be active.
  55 * FP16 needed
  56 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  57 * FCVT between 16/32/64 needed
  58 * c++11 atomics not very efficient
  59 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  60 * needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
  61
  62 # What we are *NOT* doing:
  63
  64 * A processor that is fundamentally incompatible (noncompliant) with Power.
  65  (**escape-sequencing requires and guarantees compatibility**).
  66 * Opcode 4 Signal Processing (SPE)
  67 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
  68 * Avoidable legacy opcodes
  69 * SIMD. it's awful.
  70
  71 # SimpleV
  72
  73 see [[openpower/sv]].
  74 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  75 register files to "a sequence of elements".  The **one** instruction
  76 (an unmodified **scalar** instruction) is interpreted as a *hardware
  77 for-loop* that issues **multiple** internal instructions with
  78 sequentially-incrementing register numbers.
  79
  80 Thus it is completely unnecessary to add any vector opcodes - at all -
  81 saving hugely on both hardware and compiler development time when
  82 the concept is dropped on top of a pre-existing ISA.
  83
  84 # Integer Overflow / Saturate
  85
  86 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  87
  88 # atomics
  89
  90 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  91
  92 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  93
  94 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  95
  96 # FP16
  97
  98 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  99
 100 Usually done with a fmt field, 2 bit, last one is FP128
 101
 102 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
 103
 104 # Escape Sequencing
 105
 106 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
 107 from OpenPower Foundation.
 108
 109 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
 110 (including for and by OpenPower Foundation)
 111
 112 ## Branches in namespaces
 113
 114 Branches are fine as it is up to the compiler to decide whether to let the
 115 ISAMUX/NS/escape-sequence countdown run out.
 116
 117 This is all a software / compiler / ABI issue.
 118
 119 ## Function calls in namespaces
 120
 121 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 122
 123 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 124
 125 All of this is a software issue (compiler / ABI).
 126
 127 # Compressed, 48, 64, VBLOCK
 128
 129 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 130
 131 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 132 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 133
 134 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 135 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 136 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 137 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 138
 139 Note that this requires BE instruction encoding (separate from
 140 data BE/LE encoding).  BE encoding always places the major opcode in
 141 the first 2 bytes of the raw (uninterpreted) sequential instruction
 142 byte stream.
 143
 144 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
 145 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
 146 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
 147
 148 It is not possible to distinguish LE-encoded 32-bit instructions
 149 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
 150 instructions, the opcode falls into:
 151
 152 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
 153   byte stream for a 32-bit instruction
 154 * bytes 0 and 1 for a 16-bit Compressed instruction
 155 * bytes 4 and 5 for a 48-bit SVP P48
 156 * bytes 6 and 7 for a 64-bit SVP P64
 157
 158 Clearly this is an impossible situation, therefore BE is the only
 159 option.  Note: *this is completely separate from BE/LE for data*
 160
 161 # Compressed 16
 162
 163 Further "escape-sequencing".
 164
 165 Only 11 bits available. Idea: have "pages" where one instruction selects
 166 the page number. It also specifies for how long that page is activated
 167 (terminated on a branch)
 168
 169 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 170
 171 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 172
 173 Store activation length in a CSR.
 174
 175 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 176
 177 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 178
 179 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 180
 181 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 182