openpower/sv/rfc/ls010.mdwn

   1 # RFC ls010 SVP64 Zero-Overhead Loop Prefix Subsystem
   2 **URLs**:
   3
   4 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
   5 * <https://libre-soc.org/openpower/sv/>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls010/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/64>
   9 * <https://git.openpower.foundation/isa/PowerISA/issues/121>
  10
  11 **Severity**: Major
  12
  13 **Status**: New
  14
  15 **Date**: 04 Apr 2023 v1
  16
  17 **Target**: v3.2B
  18
  19 **Source**: v3.0B
  20
  21 **Books and Section affected**:
  22
  23 ```
  24     New Book: new Zero-Overhead-Loop
  25     New Appendix, Zero-Overhead-Loop
  26 ```
  27
  28 **Summary**
  29
  30 ```
  31     Adds a Zero-Overhead-Loop Subsystem based on the Cray True-Scalable Vector concept
  32     in a RISC-paradigm fashion.  Total instructions added is six, plus Prefix format.
  33 ```
  34
  35 **Submitter**: Luke Leighton (Libre-SOC)
  36
  37 **Requester**: Libre-SOC
  38
  39 **Impact on processor**:
  40
  41 ```
  42     Addition of new "Zero-Overhead-Loop-Control" DSP-style Vector-style
  43     subsystem that in simple low-end (Embedded) systems may be minimalistically
  44     and easily be implemented by inserting a new fully-independent Pipeline Stage
  45     in between Decode and Issue, with very little disruption, and in higher
  46     performance pre-existing Multi-Issue Out-of-Order systems seamlessly fits likewise
  47     to significantly boost performance.
  48 ```
  49
  50 **Impact on software**:
  51
  52 ```
  53     Requires support for new instructions in assembler, debuggers, and related tools.
  54     Dramatically reduces instructions. Requires introduction of term "High-Level Assembler"
  55 ```
  56
  57 **Keywords**:
  58
  59 ```
  60     Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
  61     True-Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
  62     Digital Signal Processing (DSP), High-level Assembler
  63 ```
  64
  65 **Motivation**
  66
  67 Just at the time when customers are asking for higher performance,
  68 the seductive lure of SIMD, as outlined in the sigarch "SIMD Considered
  69 Harmful" article is getting out of control and damaging the reputation
  70 of mainstream general-purpose ISAs that offer it.  A solution from
  71 50 years ago exists in the form of Cray-Style True-Scalable Vectors.
  72 However the usual way that True-Scalable Vector ISAs are done *also*
  73 adds more instructions and complexifies the ISA.  Simple-V takes a step
  74 back to a simpler era in computing from half a century ago: the Zilog
  75 Z80 CPIR and LDIR instructions, and the 8086 REP instruction, and brings
  76 them forward to Modern-day Computing.  The result is a huge reduction in
  77 programming complexity, and a strong base to project the Power ISA back
  78 to the world's most powerful Supercomputing ISA for at least the next two
  79 decades.
  80
  81 **Notes and Observations**:
  82
  83 Related RFCs are [[ls008]] for the two Management instructions `setvl`
  84 and `svstep`, and [ls009]] for the REMAP Subsystem. Also [[ls001]] is
  85 a Dependency as it introduces Primary Opcode 9 64-bit encoding. An
  86 additional RFC [[ls005]] introduced XLEN on which SVP64 is also critically
  87 dependent, for Element-width Overrides.
  88
  89 **Changes**
  90
  91 Add the following entries to:
  92
  93 * A new "Vector Looping" Book
  94 * New Vector-Looping Chapters
  95 * New Vector-Looping Appendices
  96
  97 [[!tag opf_rfc]]
  98
  99 --------
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