openpower/sv/tern_bin.mdwn

   1
   2
   3 <!-- hide -->
   4 * <https://bugs.libre-soc.org/show_bug.cgi?id=1034> design/implement crfternlogi binlut etc.
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=1023> regfile analysis
   6 * <https://bugs.libre-soc.org/show_bug.cgi?id=1017> ls007 RFC
   7 <!-- show -->
   8
   9
  10 ## GPR Ternary Logic Immediate
  11
  12 Add this section to Book I 3.3.13
  13
  14 TLI-form
  15
  16 | 0-5 | 6-10 | 11-15 | 16-20 | 21-28 | 29-30 | 31 | Form     |
  17 |-----|------|-------|-------|-------|-------|----|----------|
  18 | PO  | RT   |  RA   |  RB   | TLI   | XO    | Rc | TLI-Form |
  19
  20 * `ternlogi RT, RA, RB, TLI` (`Rc=0`)
  21 * `ternlogi. RT, RA, RB, TLI` (`Rc=1`)
  22
  23 Pseudocode:
  24
  25 ```
  26     result <- (~RT & ~RA & ~RB & TLI[0]*64) | # 64 copies of TLI[0]
  27               (~RT & ~RA &  RB & TLI[1]*64) | # ...
  28               (~RT &  RA & ~RB & TLI[2]*64) |
  29               (~RT &  RA &  RB & TLI[3]*64) |
  30               ( RT & ~RA & ~RB & TLI[4]*64) |
  31               ( RT & ~RA &  RB & TLI[5]*64) |
  32               ( RT &  RA & ~RB & TLI[6]*64) | # ...
  33               ( RT &  RA &  RB & TLI[7]*64)   # 64 copies of TLI[7]
  34     RT <- result
  35 ```
  36
  37 For each integer value i, 0 to 63, do the following.
  38
  39 ```
  40     Let j be the value of the concatenation of the
  41     contents of bit i of RT, bit i of RB, bit i of RT.
  42     The value of bit j of TLI is placed into bit i of RT.
  43
  44     See Table 145, "xxeval(A, B, C, TLI) Equivalent
  45     Functions," on page 968 for the equivalent function
  46     evaluated by this instruction for any given value of TLI.
  47 ```
  48
  49 *Programmer's Note: this is a Read-Modify-Write instruction on RT.
  50 A simple copy instruction may be used to achieve the effect of
  51 3-in 1-out. The copy instruction should come immediately before
  52 `ternlogi` so that hardware may optionally Macro-Op Fuse them*
  53
  54 *Programmer's note: This instruction is useful when combined with Matrix REMAP
  55 in "Inner Product" Mode, creating Warshall Transitive Closure that has many
  56 applications in Computer Science.*
  57
  58 Special registers altered:
  59
  60 ```
  61     CR0                    (if Rc=1)
  62 ```
  63
  64 ----------
  65
  66 \newpage{}
  67
  68 ## Condition Register Ternary Logic Immediate
  69
  70 Add this section to Book I 2.5.1
  71
  72 CRB-form
  73
  74 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form     |
  75 |----|----|----|-----|-----|-----|-----|-----|---|----------|
  76 | PO | BF | msk|BFA  | msk | BFB | TLI | XO  |TLI| CRB-Form |
  77
  78 * `crternlogi BF, BFA, BFB, TLI, msk`
  79
  80 Pseudocode:
  81
  82 ```
  83     a <- CR[4*BF+32:4*BF+35]
  84     b <- CR[4*BFA+32:4*BFA+35]
  85     c <- CR[4*BFB+32:4*BFB+35]
  86     ternary <- (~a & ~b & ~c & TLI[0]*4) | # 4 copies of TLI[0]
  87                (~a & ~b &  c & TLI[1]*4) | # 4 copies of TLI[1]
  88                (~a &  b & ~c & TLI[2]*4) | # ...
  89                (~a &  b &  c & TLI[3]*4) |
  90                ( a & ~b & ~c & TLI[4]*4) |
  91                ( a & ~b &  c & TLI[5]*4) |
  92                ( a &  b & ~c & TLI[6]*4) | # ...
  93                ( a &  b &  c & TLI[7]*4))  # 4 copies of TLI[7]
  94     do i = 0 to 3
  95         if msk[i] = 1 then
  96             CR[4*BF+32+i] <- ternary[i]
  97 ```
  98
  99 For each integer value i, 0 to 3, do the following.
 100
 101 ```
 102     Let j be the value of the concatenation of the
 103     contents of bit i of CR Field BF, bit i of CR Field BFA,
 104     bit i of CR Field BFB.
 105
 106     If bit i of msk is set to 1 then the value of bit j of TLI
 107     is placed into bit i of CR Field BF.
 108
 109     Otherwise, if bit i of msk is a zero then bit i of
 110     CR Field BF is unchanged.
 111
 112     See Table 145, "xxeval(A, B, C, TLI) Equivalent
 113     Functions," on page 968 for the equivalent function
 114     evaluated by this instruction for any given value of TLI.
 115 ```
 116
 117 If `msk` is zero an Illegal Instruction trap is raised.
 118
 119 *Programmer's Note: this instruction is a "masked" overwrite on CR Field
 120 BF. For each bit set in msk a Write is performed but for each bit clear
 121 in msk the corresponding bit of BF is preserved. Overall this makes
 122 crbinlog a conditionally Read-Modify-Write instruction on CR Field BF.
 123 A simple copy instruction may be used to achieve the effect of
 124 3-in 1-out. The copy instruction should come immediately before
 125 `crternlogi` so that hardware may optionally Macro-Op Fuse them*
 126
 127 Special registers altered:
 128
 129 ```
 130     CR field BF
 131 ```
 132
 133 ----------
 134
 135 \newpage{}
 136
 137 ## GPR Dynamic Binary Logic
 138
 139 Add this section to Book I 3.3.13
 140
 141 BM2-form
 142
 143 | 0-5 | 6-10 | 11-15 | 16-20 | 21-25 | 26 | 27-31 | Form    |
 144 |-----|------|-------|-------|-------|----|-------|---------|
 145 | PO  |  RT  |  RA   |  RB   |  RC   | nh | XO    | VA-Form |
 146
 147 * `binlog RT, RA, RB, RC, nh`
 148
 149 Pseudocode:
 150
 151 ```
 152     if nh = 1 then lut <- (RC)[56:59]
 153     else           lut <- (RC)[60:63]
 154     result <- (~RA & ~RB & lut[0]*64) |
 155               (~RA &  RB & lut[1]*64) |
 156               ( RA & ~RB & lut[2]*64) |
 157               ( RA &  RB & lut[3]*64))
 158     RT <- result
 159 ```
 160
 161 For each integer value i, 0 to 63, do the following.
 162
 163 ```
 164     If nh contains a 0, let lut be the four LSBs of RC
 165     (bits 60 to 63).  Otherwise let lut be the next
 166     four LSBs of RC (bits 56 to 59).
 167
 168     Let j be the value of the concatenation of the
 169     contents of bit i of RT with bit i of RB.
 170
 171     The value of bit j of lut is placed into bit i of RT.
 172 ```
 173
 174 Special registers altered:
 175
 176 ```
 177     None
 178 ```
 179
 180 **Programmer's Note**:
 181
 182 Dynamic (non-immediate-based) Ternary Logic, suitable for FPGA-style LUT3
 183 dynamic lookups and for JIT runtime acceleration, may be emulated by
 184 appropriate combination of `binlog` and `ternlogi`, using the `nh`
 185 (next half) operand to select first and second nibble:
 186
 187 ```
 188     # compute r3 = ternlog(r4, r5, r6, table=r7)
 189     # compute the values for when r6[i] = 0:
 190     binlog r3, r4, r5, r7, 0  # takes look-up-table from LSB 4 bits
 191     # compute the values for when r6[i] = 1:
 192     binlog r4, r4, r5, r7, 1  # takes look-up-table from second-to-LSB 4 bits
 193     # mux the two results together: r3 = (r3 & ~r6) | (r4 & r6)
 194     ternlogi r3, r4, r6, 0b11011000
 195 ```
 196
 197 ----------
 198
 199 \newpage{}
 200
 201 ## Condition Register Field Dynamic Binary Logic
 202
 203 Add this section to Book I 2.5.1
 204
 205 CRB-form
 206
 207 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form     |
 208 |----|----|----|-----|-----|-----|-----|-----|---|----------|
 209 | PO | BF | msk|BFA  | msk | BFB | //  | XO  |// | CRB-Form |
 210
 211 * `crbinlog BF, BFA, BFB, msk`
 212
 213 Pseudocode:
 214
 215 ```
 216     a <- CR[4*BF+32:4*BFA+35]
 217     b <- CR[4*BFA+32:4*BFA+35]
 218     lut <- CR[4*BFB+32:4*BFB+35]
 219     binary <- (~a & ~b & lut[0]*4) |
 220               (~a &  b & lut[1]*4) |
 221               ( a & ~b & lut[2]*4) |
 222               ( a &  b & lut[3]*4))
 223     do i = 0 to 3
 224         if msk[i] = 1 then
 225             CR[4*BF+32+i] <- binary[i]
 226 ```
 227
 228 For each integer value i, 0 to 3, do the following.
 229
 230 ```
 231     Let j be the value of the concatenation of the
 232     contents of bit i of CR Field BF with bit i of CR Field BFA.
 233
 234     If bit i of msk is set to 1 then the value of bit j of
 235     CR Field BFB is placed into bit i of CR Field BF.
 236
 237     Otherwise, if bit i of msk is a zero then bit i of
 238     CR Field BF is unchanged.
 239 ```
 240
 241 If `msk` is zero an Illegal Instruction trap is raised.
 242
 243 Special registers altered:
 244
 245 ```
 246     CR field BF
 247 ```
 248
 249 *Programmer's Note: just as with binlut and ternlogi, a pair
 250  of crbinlog instructions followed by a merging crternlogi may
 251  be deployed to synthesise dynamic ternary (LUT3) CR Field
 252  manipulation*
 253
 254 *Programmer's Note: this instruction is a "masked" overwrite on CR
 255 Field BF. For each bit set in `msk` a Write is performed
 256 but for each bit clear in `msk` the corresponding bit of BF is
 257 preserved. Overall this makes `crbinlog` a conditionally
 258 Read-Modify-Write instruction on CR Field BF.
 259 A simple copy instruction may be used to achieve the effect of
 260 3-in 1-out. The copy instruction should come immediately before
 261 `crternlogi` so that hardware may optionally Macro-Op Fuse them*
 262
 263 [[!tag standards]]
 264
 265 ----------
 266
 267 \newpage{}
 268