4 * <https://bugs.libre-soc.org/show_bug.cgi?id=1034> design/implement crfternlogi binlut etc.
5 * <https://bugs.libre-soc.org/show_bug.cgi?id=1023> regfile analysis
6 * <https://bugs.libre-soc.org/show_bug.cgi?id=1017> ls007 RFC
10 ## GPR Ternary Logic Immediate
12 Add this section to Book I 3.3.13
16 TLI 0.5 | 6.10 | 11.15 | 16.20 | 21.28 | 29.30 | 31 | Form |
17 |-------|------|-------|-------|-------|-------|----|----------|
18 | PO | RT | RA | RB | TLI | XO | Rc | TLI-Form |
20 * `ternlogi RT, RA, RB, TLI` (`Rc=0`)
21 * `ternlogi. RT, RA, RB, TLI` (`Rc=1`)
26 result <- (~RT & ~RA & ~RB & TLI[0]*64) | # 64 copies of TLI[0]
27 (~RT & ~RA & RB & TLI[1]*64) | # ...
28 (~RT & RA & ~RB & TLI[2]*64) |
29 (~RT & RA & RB & TLI[3]*64) |
30 ( RT & ~RA & ~RB & TLI[4]*64) |
31 ( RT & ~RA & RB & TLI[5]*64) |
32 ( RT & RA & ~RB & TLI[6]*64) | # ...
33 ( RT & RA & RB & TLI[7]*64) # 64 copies of TLI[7]
37 For each integer value i, 0 to 63, do the following.
40 Let j be the value of the concatenation of the
41 contents of bit i of RT, bit i of RB, bit i of RT.
42 The value of bit j of TLI is placed into bit i of RT.
44 See Table 145, "xxeval(A, B, C, TLI) Equivalent
45 Functions," on page 968 for the equivalent function
46 evaluated by this instruction for any given value of TLI.
49 *Programmer's Note: this is a Read-Modify-Write instruction on RT.
50 A simple copy instruction may be used to achieve the effect of
51 3-in 1-out. The copy instruction should come immediately before
52 `ternlogi` so that hardware may optionally Macro-Op Fuse them*
54 *Programmer's note: This instruction is useful when combined with Matrix REMAP
55 in "Inner Product" Mode, creating Warshall Transitive Closure that has many
56 applications in Computer Science.*
58 Special registers altered:
68 ## Condition Register Field Ternary Logic Immediate
70 Add this section to Book I 2.5.1
74 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form |
75 |----|----|----|-----|-----|-----|-----|-----|---|----------|
76 | PO | BF | msk|BFA | msk | BFB | TLI | XO |TLI| CRB-Form |
78 * `crfternlogi BF, BFA, BFB, TLI, msk`
83 a <- CR[4*BF+32:4*BF+35]
84 b <- CR[4*BFA+32:4*BFA+35]
85 c <- CR[4*BFB+32:4*BFB+35]
86 ternary <- (~a & ~b & ~c & TLI[0]*4) | # 4 copies of TLI[0]
87 (~a & ~b & c & TLI[1]*4) | # 4 copies of TLI[1]
88 (~a & b & ~c & TLI[2]*4) | # ...
89 (~a & b & c & TLI[3]*4) |
90 ( a & ~b & ~c & TLI[4]*4) |
91 ( a & ~b & c & TLI[5]*4) |
92 ( a & b & ~c & TLI[6]*4) | # ...
93 ( a & b & c & TLI[7]*4)) # 4 copies of TLI[7]
96 CR[4*BF+32+i] <- ternary[i]
99 For each integer value i, 0 to 3, do the following.
102 Let j be the value of the concatenation of the
103 contents of bit i of CR Field BF, bit i of CR Field BFA,
104 bit i of CR Field BFB.
106 If bit i of msk is set to 1 then the value of bit j of TLI
107 is placed into bit i of CR Field BF.
109 Otherwise, if bit i of msk is a zero then bit i of
110 CR Field BF is unchanged.
112 See Table 145, "xxeval(A, B, C, TLI) Equivalent
113 Functions," on page 968 for the equivalent function
114 evaluated by this instruction for any given value of TLI.
117 If `msk` is zero an Illegal Instruction trap is raised.
119 *Programmer's Note: this instruction is a "masked" overwrite on CR Field
120 BF. For each bit set in msk a Write is performed but for each bit clear
121 in msk the corresponding bit of BF is preserved. Overall this makes
122 crbinlog a conditionally Read-Modify-Write instruction on CR Field BF.
123 A simple copy instruction may be used to achieve the effect of
124 3-in 1-out. The copy instruction should come immediately before
125 `crternlogi` so that hardware may optionally Macro-Op Fuse them*
127 Special registers altered:
137 ## Condition Register Ternary Logic Immediate
139 Add this section to Book I 2.5.1
143 TLI 0.5 | 6.10 | 11.15 | 16.20 | 21.28 | 29.31 | Form |
144 |-------|------|-------|-------|-------|-------|----------|
145 | PO | BT | BA | BB | TLI | XO | TLI-Form |
147 * `crternlogi BT, BA, BB, TLI`
152 idx <- CR[BT+32] || CR[BA+32] || CR[BB+32]
153 CR[4*BT+32] <- TLI[7-idx]
156 Special registers altered:
166 ## GPR Dynamic Binary Logic
168 Add this section to Book I 3.3.13
172 | 0-5 | 6-10 | 11-15 | 16-20 | 21-25 | 26 | 27-31 | Form |
173 |-----|------|-------|-------|-------|----|-------|---------|
174 | PO | RT | RA | RB | RC | nh | XO | VA-Form |
176 * `binlog RT, RA, RB, RC, nh`
181 if nh = 1 then lut <- (RC)[56:59]
182 else lut <- (RC)[60:63]
183 result <- (~RA & ~RB & lut[0]*64) |
184 (~RA & RB & lut[1]*64) |
185 ( RA & ~RB & lut[2]*64) |
186 ( RA & RB & lut[3]*64))
190 For each integer value i, 0 to 63, do the following.
193 If nh contains a 0, let lut be the four LSBs of RC
194 (bits 60 to 63). Otherwise let lut be the next
195 four LSBs of RC (bits 56 to 59).
197 Let j be the value of the concatenation of the
198 contents of bit i of RT with bit i of RB.
200 The value of bit j of lut is placed into bit i of RT.
203 Special registers altered:
209 **Programmer's Note**:
211 Dynamic (non-immediate-based) Ternary Logic, suitable for FPGA-style LUT3
212 dynamic lookups and for JIT runtime acceleration, may be emulated by
213 appropriate combination of `binlog` and `ternlogi`, using the `nh`
214 (next half) operand to select first and second nibble:
217 # compute r3 = ternlog(r4, r5, r6, table=r7)
218 # compute the values for when r6[i] = 0:
219 binlog r3, r4, r5, r7, 0 # takes look-up-table from LSB 4 bits
220 # compute the values for when r6[i] = 1:
221 binlog r4, r4, r5, r7, 1 # takes look-up-table from second-to-LSB 4 bits
222 # mux the two results together: r3 = (r3 & ~r6) | (r4 & r6)
223 ternlogi r3, r4, r6, 0b11011000
230 ## Condition Register Field Dynamic Binary Logic
232 Add this section to Book I 2.5.1
236 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form |
237 |----|----|----|-----|-----|-----|-----|-----|---|----------|
238 | PO | BF | msk|BFA | msk | BFB | // | XO |// | CRB-Form |
240 * `crfbinlog BF, BFA, BFB, msk`
245 a <- CR[4*BF+32:4*BFA+35]
246 b <- CR[4*BFA+32:4*BFA+35]
247 lut <- CR[4*BFB+32:4*BFB+35]
248 binary <- (~a & ~b & lut[0]*4) |
249 (~a & b & lut[1]*4) |
250 ( a & ~b & lut[2]*4) |
254 CR[4*BF+32+i] <- binary[i]
257 For each integer value i, 0 to 3, do the following.
260 Let j be the value of the concatenation of the
261 contents of bit i of CR Field BF with bit i of CR Field BFA.
263 If bit i of msk is set to 1 then the value of bit j of
264 CR Field BFB is placed into bit i of CR Field BF.
266 Otherwise, if bit i of msk is a zero then bit i of
267 CR Field BF is unchanged.
270 If `msk` is zero an Illegal Instruction trap is raised.
272 Special registers altered:
278 *Programmer's Note: just as with binlut and ternlogi, a pair
279 of crbinlog instructions followed by a merging crternlogi may
280 be deployed to synthesise dynamic ternary (LUT3) CR Field
283 *Programmer's Note: this instruction is a "masked" overwrite on CR
284 Field BF. For each bit set in `msk` a Write is performed
285 but for each bit clear in `msk` the corresponding bit of BF is
286 preserved. Overall this makes `crbinlog` a conditionally
287 Read-Modify-Write instruction on CR Field BF.
288 A simple copy instruction may be used to achieve the effect of
289 3-in 1-out. The copy instruction should come immediately before
290 `crternlogi` so that hardware may optionally Macro-Op Fuse them*
292 ## Condition Register Dynamic Binary Logic
294 Add this section to Book I 2.5.1
298 | 0.5|6.10|11.15|16.20|21.30| 31| Form |
299 |----|----|-----|-----|-----|---|----------|
300 | PO | BT | BA | BB | XO | / | CRB-Form |
302 * `crbinlog BF, BFA, BFB, msk`
307 lut <- CR[4*BFB+32:4*BFB+35]
308 idx <- CR[BT+32] || CR[BA+32]
309 CR[BT+32] <- lut[3-idx]
312 Special registers altered:
318 *Programmer's Note: just as with binlut and ternlogi, a pair
319 of crbinlog instructions followed by a merging crternlogi may
320 be deployed to synthesise dynamic ternary (LUT3) CR Field