shakti/m_class/DDR.mdwn

   1 # DDR (DRAM) Controller and PHY
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   3 * <https://github.com/enjoy-digital/litedram> - controller inc. DDR3 / LPDDR3
   4 * <https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki> - CERN DDR3 ctrl
   5 * <https://www.linkedin.com/in/michael-taylor-32212816/> working on DDR3 IO Cells
   6 * <https://github.com/waviousllc/wav-lpddr-hw>
   7 * <https://github.com/ZiyangYE/General-Slow-DDR3-Interface>
   8 * <https://github.com/ultraembedded/core_ddr3_controller>
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