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[libreriscv.git] / shakti / m_class / libre_3d_gpu.mdwn
1 # Libre 3D GPU Requirements
2
3 ## GPU capabilities
4
5 Based on GC800 the following would be acceptable performance (as would
6 Mali-400):
7
8 * 35 million triangles/sec
9 * 325 milllion pixels/sec
10 * 6 GFLOPS
11
12 ## GPU size and power
13
14 * Basically the power requirement should be at or below around 1 watt
15 in 40nm. Beyond 1 watt it becomes... difficult.
16 * Size is not particularly critical as such but should not be insane.
17
18 Based on GC800 the following would be acceptable area in 40nm:
19
20 * 1.9mm^2 synthesis area
21 * 2.5mm^2 silicon area.
22
23 So here's a table showing embedded cores:
24
25 <https://www.cnx-software.com/2013/01/19/gpus-comparison-arm-mali-vs-vivante-gcxxx-vs-powervr-sgx-vs-nvidia-geforce-ulp/>
26
27 Silicon area corresponds *ROUGHLY* with power usage, but PLEASE do
28 not take that as absolute, because if you read Jeff's Nyuzi 2016 paper
29 you'll see that getting data through the L1/L2 cache barrier is by far
30 and above the biggest eater of power.
31
32 Note lower down that the numbers for Mali-400 are for the *4* core
33 version - Mali-400 (MP4) - where Jeff and I compared Mali-400 SINGLE CORE
34 and discovered that Nyuzi, if 4 parallel Nyuzi cores were put
35 together, would reach only 25% of Mali-400's performance (in about the
36 same silicon area).
37
38 ## Other
39
40 * The deadline is about 12-18 months.
41 * It is highly recommended to use Gallium3D for the software stack
42 (see below if deciding whether to use Nyuzi or RISC-V or other)
43 * Software must be licensed under LGPLv2+ or BSD/MIT.
44 * Hardware (RTL) must be licensed under BSD or MIT with no
45 "NON-COMMERCIAL" CLAUSES.
46 * Any proposals will be competing against Vivante GC800 (using Etnaviv driver).
47 * The GPU is integrated (like Mali-400). So all that the GPU needs
48 to do is write to an area of memory (framebuffer or area of the
49 framebuffer). The SoC - which in this case has a RISC-V core and has
50 peripherals such as the LCD controller - will take care of the rest.
51 * In this arcitecture, the GPU, the CPU and the peripherals are all on
52 the same AXI4 shared memory bus. They all have access to the same shared
53 DDR3/DDR4 RAM. So as a result the GPU will use AXI4 to write directly
54 to the framebuffer and the rest will be handle by SoC.
55 * The job must be done by a team that shows sufficient expertise to
56 reduce the risk.
57
58 ## Notes
59
60 * The deadline is really tight. If an FPGA (or simulation) plus the basics
61 of the software driver are at least prototyped by then it *might* be ok.
62 * If using Nyuzi as the basis it *might* be possible to begin the
63 software port in parallel because Jeff went to the trouble of writing
64 a cycle-accurate simulation.
65 * I *suspect* it will result in less work to use Gallium3D than, for
66 example, writing an entire OpenGL stack from scratch.
67 * A *demo* should run on an FPGA as an initial. The FPGA is not a priority
68 for assessment, but it would be *nice* if it could fit into a ZC706.
69 * Also if there is parallel hardware obviously it would be nice to be able
70 to demonstrate parallelism to the maximum extend possible. But again,
71 being reasonable, if the GPU is so big that only a single core can fit
72 into even a large FPGA then for an initial demo that would be fine.
73 * Note that no other licenses are acceptable for the hardware: all GPL
74 licenses (GPL, AGPL, LGPL) are out. GPL (all revisions v2, v3, v2+, v3+)
75 are out for software, with the exception of the LGPL (v2+ or v3+ acceptable).
76
77 ## Design decisions and considerations
78
79 Whilst Nyuzi has a big advantage in that it has simuations and also a
80 llvm port and so on, if utilised for this particular RISC-V chip it would
81 mean needing to write a "memory shim" between the general-purpose Nyuzi
82 core and the main processor, i.e. all the shader info, state etc. needs
83 synchronisation hardware (and software). That could significantly
84 complicate design, especially of software.
85
86 Whilst i *recommended* Gallium3D there is actually another possible approach:
87
88 A RISC-V multi-core design which accelerates *software*
89 rendering... including potentially utilising the fact that Gallium3D
90 has a *software* (LLVM) renderer:
91
92 <https://mesa3d.org/llvmpipe.html>
93
94 The general aim of this approach is *not* to have the complexity of
95 transferring significant amounts of data structures to and from disparate
96 cores (one Nyuzi, one RISC-V) but to STAY WITHIN THE RISC-V ARCHITECTURE
97 and simply compile Mesa3D (for RISC-V), gallium3d-llvm (for RISC-V),
98 modifying llvm for RISC-V to do the heavy-lifting instead.
99
100 Then it just becomes a matter of adding Vector/SIMD/Parallelization
101 extensions to RISC-V, and adding support in LLVM for the same:
102
103 <https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html>
104
105 So if considering to base the design on RISC-V, that means turning RISC-V
106 into a vector processor. Now, whilst Hwacha has been located (finally),
107 it's a design that is specifically targetted at supercomputers. I have
108 been taking an alternative approach to vectorisation which is more about
109 *parallelization* than it is about *vectorization*.
110
111 It would be great for Simple-V to be given consideration for
112 implementation as the abstraction "API" of Simple-V would greatly simplify
113 the addition process of Custom features such as fixed-function pixel
114 conversion and rasterization instructions (if those are chosen to be
115 added) and so on. Bear in mind that a high-speed clock rate is NOT a
116 good idea for GPUs (power being a square law), multi-core parallelism
117 and longer SIMD/vectors are much better to consider, instead.
118
119 The PDF/slides on Simple-V is here:
120
121 <http://hands.com/~lkcl/simple_v_chennai_2018.pdf>
122
123 And the assessment, design and implementation is being done here:
124
125 <http://libre-riscv.org/simple_v_extension/>
126
127 ----
128
129 My feeling on this is therefore that the following approach is one which involve minimal work:
130
131 * Investigate the ChiselGPU code to see if it can be leveraged (an
132 "image" added instead of straight ARGB color).
133 * OR... add sufficient fixed-function 3D instructions (plus a memory
134 scratch area) to RISC-V to do the equivalent job.
135 * Implement the Simple-V RISC-V "parallelism" extension (which can
136 parallelize xBitManip *and* the above-suggested 3D fixed-function
137 instructions).
138 * Wait for RISC-V LLVM to have vectorization support added to it.
139 * MODIFY the resultant RISC-V LLVM code so that it supports Simple-V.
140 * Grab the gallium3d-llvm source code and hit the "compile" button.
141 * Grab the *standard* Mesa3D library, tell it to use the gallium3d-llvm library and hit the "compile" button.
142 * see what happens.
143
144 Now, interestingly, if spike is thrown into the mix there (as a
145 cycle-accurate RISC-V simulator) it should be perfectly well possible to
146 get an idea of where performance of the above would need optimization,
147 just like Jeff did with the Nyuzi paper.
148
149 He focussed on specific algorithms and checked the assembly code, and
150 worked out how many instruction cycles per pixel were needed, which is
151 an invaluable measure.
152
153 As I mention in the above page, one of the problems with doing a
154 completely separate engine (Nyuzi is actually a general-purpose RISC-based
155 vector processor) is that when it comes to using it, you need to transfer
156 all the "state" data structures from the main core over to the GPU's core.
157
158 ... But if the main core is RISC-V *and the GPU is RISC-V as well*
159 and they are SMP cores then transferring the state is a simple matter of
160 doing a context-switch... or if *all* cores have vector and 3D instruction
161 extensions, a context-switch is not needed at all.
162
163 Will that approach work? Honestly I have absolutely no idea, but it
164 would be a fascinating and extremely ambitious research project.
165
166 Can we get people to fund it? Yeah I do. there's a lot of buzz about
167 RISC-V, and a lot of buzz can be created about a libre 3D GPU. If that
168 same GPU happens to be good at doing crypto-currency mining there will be
169 a LOT more attention paid, particularly given that people have noticed
170 that relying on proprietary GPUs and CPUs to manage billions of dollars
171 worth of crypto-currency, when the NSA is *known* to have blackmailed
172 intel into putting a spying back-door co-processor in to x86, and that
173 it miiight not be a good idea to trust proprietary hardware:
174
175 <http://libreboot.org/faq#intelme>
176
177 ## Q & A
178
179 > Q:
180 >
181 > Do you need a team with good CVs? What about if the team shows you
182 > an acceptable FPGA prototype? I’m talking about a team of students
183 > which do not have big industrial CVs but they know how to handle this
184 > job (just like RocketChip or MIAOW or etc…).
185
186 A:
187
188 That would be fantastic as it would demonstrate not only competence but
189 also commitment. And will have taken out the "risk" of being "unknown",
190 entirely. So that works perfectly for me :) .
191
192 > Q:
193 >
194 > Is there any guarantee that there would be a sponsorship for the GPU?
195
196 A:
197
198 Please please let's be absolutely clear:
199
200 I can put the *business case* to the anonymous sponsor to *consider*
201 sponsoring a libre GPU, *only* and purely on the basis of a *commercial*
202 decision based on cost and risk analysis, comparing against the best
203 alternative option which is USD $250,000 for a one-time proprietary
204 license for Vivante GC800 using etnaviv. So as a result we need to be
205 *really clear* that *there is no "guaranteed sponsorship"*. this is a
206 pure commercial *business* assessment.
207
208 However, it just so happens that there's quite a lot of people who are
209 pissed at how things go in the 3D embedded space. That can be leveraged,
210 by way of a crowd-funding campaign, to invite people to help, put money
211 behind this that has *nothing to do with the libre-riscv anonymous
212 sponsor*.