simple_v_extension/simple_add_example.mdwn

   1     function op_add(rd, rs1, rs2) # add not VADD!
   2       int i, id=0, irs1=0, irs2=0;
   3       predval = get_pred_val(FALSE, rd);
   4       rd  = int_vec[rd ].isvector ? int_vec[rd ].regidx : rd;
   5       rs1 = int_vec[rs1].isvector ? int_vec[rs1].regidx : rs1;
   6       rs2 = int_vec[rs2].isvector ? int_vec[rs2].regidx : rs2;
   7       for (i = 0; i < VL; i++)
   8         STATE.srcoffs = i # save context
   9         if (predval & 1<<i) # predication uses intregs
  10            ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
  11            if (!int_vec[rd ].isvector) break;
  12         if (int_vec[rd ].isvector)  { id += 1; }
  13         if (int_vec[rs1].isvector)  { irs1 += 1; }
  14         if (int_vec[rs2].isvector)  { irs2 += 1; }
  15         if (id == VL or irs1 == VL or irs2 == VL) {
  16           # end VL hardware loop
  17           STATE.srcoffs = 0; # reset
  18           STATE.ssvoffs = 0; # reset
  19           return;
  20         }