simple_v_extension/sv_prefix_proposal.rst

   1 [[!tag oldstandards]]
   2
   3 SimpleV Prefix (SVprefix) Proposal v0.3
   4 =======================================
   5
   6 * Copyright (c) Jacob Lifshay, 2019
   7 * Copyright (c) Luke Kenneth Casson Leighton, 2019
   8
   9 This proposal is designed to be able to operate without SVorig, but not to
  10 require the absence of SVorig. See Specification_.
  11
  12 Principle: SVprefix embeds (unmodified) RVC and 32-bit scalar opcodes
  13 into 32, 48 and 64 bit RV formats, to provide Vectorisation context
  14 on a per-instruction basis.
  15
  16 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
  17 .. _Appendix: http://libre-riscv.org/simple_v_extension/appendix/
  18
  19 .. contents::
  20
  21 Conventions
  22 ===========
  23
  24 Conventions used in this document:
  25
  26 * Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
  27 * Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
  28 * Operations work on variable-length vectors of sub-vectors up to *VL*
  29   in length, where each sub-vector has a length *svlen*, and *svlen*
  30   elements of type *etype*.
  31 * The actual total number of elements is therefore *svlen* times *VL*.
  32 * When the vectors are stored in registers, all elements are packed so
  33   that there is no padding in-between elements of the same vector.
  34 * The register file itself is thus best viewed as a byte-level SRAM that
  35   is typecast to an array of *etypes*
  36 * The number of bytes in a sub-vector, *svsz*, is the product of *svlen*
  37   and the element size in bytes.
  38
  39 Options
  40 =======
  41
  42 The following partial / full implementation options are possible:
  43
  44 * SVPrefix augments the main Specification_
  45 * SVPrefix operates independently, without the main spec VL (and MVL)
  46   CSRs (in any priv level)
  47 * SVPrefix operates independently, without the main spec SUBVL CSRs
  48   (in any priv level)
  49 * SVPrefix has no support for VL (or MVL) overrides in the 64 bit
  50   instruction format (VLtyp=0 as the only legal permitted value)
  51 * SVPrefix has no support for svlen overrides in either the 48 or 64
  52   bit instruction format either (svlen=0 as the only legal permitted value).
  53
  54 All permutations of the above options are permitted, and the UNIX
  55 platform must raise illegal instruction exceptions on implementations
  56 that do not support each option.  For example, an implementation that
  57 has no support for VLtyp that sees an opcode with a nonzero VLtyp must
  58 raise an illegal instruction exception.
  59
  60 Note that SVPrefix (VLtyp and svlen) has its own STATE CSR, SVPSTATE. This allows Prefixed operations to be re-entrant on traps, and to not affect VBLOCK use of VL or SUBVL.
  61
  62 If the main Specification_ CSRs and features are to be supported (VBLOCK), then when VLtyp or svlen are "default" they utilise the main Specification_ VBLOCK VL and/or SUBVL, and, correspondingly, the main VBLOCK STATE CSR will be updated and used to track hardware loops.
  63
  64 If however VLtyp is set to nondefault, then the SVPSTATE src and destoffs fields are used instead to create the hardware loops, and likewise if svlen is set to nondefault, SVPSTATE's svoffs field is used.
  65
  66 Half-Precision Floating Point (FP16)
  67 ====================================
  68
  69 If the F extension is supported, SVprefix adds support for FP16 in the
  70 base FP instructions by using 10 (H) in the floating-point format field
  71 *fmt* and using 001 (H) in the floating-point load/store *width* field.
  72
  73 Compressed Instructions
  74 =======================
  75
  76 Compressed instructions are under evaluation by taking the same
  77 prefix as used in P48, embedding that and standard RVC opcodes (minus
  78 their RVC prefix) into a 32-bit space.  This by taking the three remaining
  79 Major "custom" opcodes (0-2), one for each of the three RVC Quadrants.
  80 see [[discussion]].
  81
  82 48-bit Prefixed Instructions
  83 ============================
  84
  85 All 48-bit prefixed instructions contain a 32-bit "base" instruction as
  86 the last 4 bytes. Since all 32-bit instructions have bits 1:0 set to
  87 11, those bits are reused for additional encoding space in the 48-bit
  88 instructions.
  89
  90 64-bit Prefixed Instructions
  91 ============================
  92
  93 The 48 bit format is further extended with the full 128-bit range on all
  94 source and destination registers, and the option to set both SVSTATE.VL and SVSTATE.MVL
  95 is provided.
  96
  97 48-bit Instruction Encodings
  98 ============================
  99
 100 In the following table, *Rsvd* (reserved) entries must be zero.  RV32 equivalent
 101 encodings included for side-by-side comparison (and listed below,
 102 separately).
 103
 104 First, bits 17:0:
 105
 106 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 107 | Encoding      | 17     | 16     | 15       | 14  | 13     | 12          | 11:7 | 6      | 5:0    |
 108 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 109 | P48-LD-type   | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 110 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 111 | P48-ST-type   |vitp7[6]| rs1[5] | rs2[5]   | vs2 | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 112 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 113 | P48-R-type    | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | vitp6              | *Rsvd* | 011111 |
 114 +---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
 115 | P48-I-type    | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 116 +---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
 117 | P48-U-type    | rd[5]  | *Rsvd* | *Rsvd*   | vd  | *Rsvd* | vitp6              | *Rsvd* | 011111 |
 118 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 119 | P48-FR-type   | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | *Rsvd*      | vtp5 | *Rsvd* | 011111 |
 120 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 121 | P48-FI-type   | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 122 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 123 | P48-FR4-type  | rd[5]  | rs1[5] | rs2[5]   | vs2 | rs3[5] | vs3 [#fr4]_ | vtp5 | *Rsvd* | 011111 |
 124 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 125
 126 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding
 127           because there is not enough space for vs1 as well, and because
 128           it is more useful to have a scalar argument for each of the
 129           multiplication and addition portions of fmadd than to have
 130           two scalars on the multiplication portion.
 131
 132 Table showing correspondance between P48-*-type and RV32-*-type.
 133 These are bits 47:18 (RV32 shifted up by 16 bits):
 134
 135 +---------------+---------------+
 136 | Encoding      | RV32 Encoding |
 137 +---------------+---------------+
 138 | 47:32         | 31:2          |
 139 +---------------+---------------+
 140 | P48-LD-type   | RV32-I-type   |
 141 +---------------+---------------+
 142 | P48-ST-type   | RV32-S-Type   |
 143 +---------------+---------------+
 144 | P48-R-type    | RV32-R-Type   |
 145 +---------------+---------------+
 146 | P48-I-type    | RV32-I-Type   |
 147 +---------------+---------------+
 148 | P48-U-type    | RV32-U-Type   |
 149 +---------------+---------------+
 150 | P48-FR-type   | RV32-FR-Type  |
 151 +---------------+---------------+
 152 | P48-FI-type   | RV32-I-Type   |
 153 +---------------+---------------+
 154 | P48-FR4-type  | RV32-FR4-type |
 155 +---------------+---------------+
 156
 157 Table showing Standard RV32 encodings:
 158
 159 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 160 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1:0    |
 161 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 162 | RV32-R-type   +    funct7           + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 163 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 164 | RV32-S-type   + imm[11:5]           + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 0b11   |
 165 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 166 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 167 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 168 | RV32-U-type   + imm[31:12]                                         | rd[4:0]  + opcode + 0b11   |
 169 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 170 | RV32-FR4-type + rs3[4:0]    + fmt   + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 171 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 172 | RV32-FR-type  + funct5      + fmt   + rs2[4:0] + rs1[4:0] + rm     | rd[4:0]  + opcode + 0b11   |
 173 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 174
 175 64-bit Instruction Encodings
 176 ============================
 177
 178 Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6,
 179 this is now set to "0b0111111".
 180
 181 +---------------+---------------+--------------+-----------+
 182 | 63:48         | 47:18         | 17:7         | 6:0       |
 183 +---------------+---------------+--------------+-----------+
 184 | 64 bit prefix | RV32[31:3]    | P48[17:7]    | 0b0111111 |
 185 +---------------+---------------+--------------+-----------+
 186
 187 * The 64 bit prefix format is below
 188 * Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
 189 * Bits 7 to 17 contain bits 7 through 17 of the P48 format
 190 * Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
 191
 192 64 bit prefix format:
 193
 194 +--------------+-------+--------+--------+--------+--------+
 195 | Encoding     | 63    | 62     | 61     | 60     | 59:48  |
 196 +--------------+-------+--------+--------+--------+--------+
 197 | P64-LD-type  | rd[6] | rs1[6] |        | *Rsvd* | VLtyp  |
 198 +--------------+-------+--------+--------+--------+--------+
 199 | P64-ST-type  |       | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 200 +--------------+-------+--------+--------+--------+--------+
 201 | P64-R-type   | rd[6] | rs1[6] | rs2[6] | vd     | VLtyp  |
 202 +--------------+-------+--------+--------+--------+--------+
 203 | P64-I-type   | rd[6] | rs1[6] |        | *Rsvd* | VLtyp  |
 204 +--------------+-------+--------+--------+--------+--------+
 205 | P64-U-type   | rd[6] |        |        | *Rsvd* | VLtyp  |
 206 +--------------+-------+--------+--------+--------+--------+
 207 | P64-FR-type  |       | rs1[6] | rs2[6] | vd     | VLtyp  |
 208 +--------------+-------+--------+--------+--------+--------+
 209 | P64-FI-type  | rd[6] | rs1[6] | rs2[6] | vd     | VLtyp  |
 210 +--------------+-------+--------+--------+--------+--------+
 211 | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp  |
 212 +--------------+-------+--------+--------+--------+--------+
 213
 214 The extra bit for src and dest registers provides the full range of
 215 up to 128 registers, when combined with the extra bit from the 48 bit
 216 prefix as well.  VLtyp encodes how (whether) to set SVPSTATE.VL and SVPSTATE.MAXVL.
 217
 218 VLtyp field encoding
 219 ====================
 220
 221 NOTE: VL and MVL below are local to SVPrefix and, if non-default,
 222 will update the src and dest element offsets in SVPSTATE, not the main
 223 Specification_ STATE. If default (all zeros) then STATE VL and MVL apply
 224 to this instruction, and STATE.srcoffs (etc) will be used.
 225
 226 +-----------+-------------+--------------+----------+----------------------+
 227 | VLtyp[11] | VLtyp[10:6] | VLtyp[5:1]   | VLtyp[0] | comment              |
 228 +-----------+-------------+--------------+----------+----------------------+
 229 | 0         |  00000      | 00000        |  0       | no change to VL/MVL  |
 230 +-----------+-------------+--------------+----------+----------------------+
 231 | 0         |  VLdest     | VLEN         |  vlt     | VL imm/reg mode (vlt)|
 232 +-----------+-------------+--------------+----------+----------------------+
 233 | 1         |  VLdest     | MVL+VL-immed | 0        | MVL+VL immed mode    |
 234 +-----------+-------------+--------------+----------+----------------------+
 235 | 1         |  VLdest     |  MVL-immed   | 1        | MVL immed mode       |
 236 +-----------+-------------+--------------+----------+----------------------+
 237
 238 Note: when VLtyp is all zeros, the main Specification_ VL and MVL apply
 239 to this instruction. If called outside of a VBLOCK or if sv.setvl has
 240 not set VL, the operation is "scalar".
 241
 242 Just as in the VBLOCK format, when bit 11 of VLtyp is zero:
 243
 244 * if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
 245   (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
 246 * if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
 247   from which VL is set.  x0 is not permitted
 248 * VL goes into the scalar register VLdest (if VLdest is not x0)
 249
 250 When bit 11 of VLtype is 1:
 251
 252 * if VLtyp[0] is zero, both SVPSTATE.MAXVL and SVPSTATE.VL are set to (imm+1).  The same
 253   value goes into the scalar register VLdest (if VLdest is not x0)
 254 * if VLtyp[0] is 1, SVPSTATE.MAXVL is set to (imm+1).
 255   SVPSTATE.VL will be truncated to within the new range (if VL was greater
 256   than the new MAXVL).  The new VL goes into the scalar register VLdest
 257   (if VLdest is not x0).
 258
 259 This gives the option to set up SVPSTATE.VL in a "loop mode" (VLtype[11]=0) or
 260 in a "one-off" mode (VLtype[11]=1) which sets both MVL and VL to the
 261 same immediate value.  This may be most useful for one-off Vectorised
 262 operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
 263 of large batches of registers in context-switches or function calls.
 264
 265 Note that VLtyp's VL and MVL are not the same as the main Specification_
 266 VL or MVL, and that loops will alter srcoffs and destoffs in SVPSTATE in VLtype nondefault mode, but the srcoffs and destoffs in STATE, if VLtype=0.
 267
 268 Furthermore, the execution order and exception handling must be exactly
 269 the same as in the main spec (Program Order must be preserved)
 270
 271 Pseudocode for SVPSTATE.VL:
 272
 273 .. parsed-literal::
 274
 275     # pseudocode
 276
 277     regs = [0u64; 128];
 278     vl = 0;
 279
 280     // instruction fields:
 281     rd = get_rd_field();
 282     vlmax = get_immed_field();
 283
 284     // handle illegal instruction decoding
 285     if vlmax > XLEN {
 286         trap()
 287     }
 288
 289     // calculate VL
 290     if rs1 == 0 { // rs1 is x0
 291         vl = vlmax
 292     } else {
 293         vl = min(regs[rs1], vlmax)
 294     }
 295
 296     // write rd
 297     if rd != 0 {
 298         // rd is not x0
 299         regs[rd] = vl
 300     }
 301
 302 vs#/vd Fields' Encoding
 303 =======================
 304
 305 +--------+----------+----------------------------------------------------------+
 306 | vs#/vd | Mnemonic | Meaning                                                  |
 307 +========+==========+==========================================================+
 308 | 0      | S        | the rs#/rd field specifies a scalar (single sub-vector); |
 309 |        |          | the rs#/rd field is zero-extended to get the actual      |
 310 |        |          | 7-bit register number                                    |
 311 +--------+----------+----------------------------------------------------------+
 312 | 1      | V        | the rs#/rd field specifies a vector; the rs#/rd field is |
 313 |        |          | decoded using the `Vector Register Number Encoding`_ to  |
 314 |        |          | get the actual 7-bit register number                     |
 315 +--------+----------+----------------------------------------------------------+
 316
 317 If a vs#/vd field is not present, it is as if it was present with a value that
 318 is the bitwise-or of all present vs#/vd fields.
 319
 320 * scalar register numbers do NOT increment when allocated in the
 321   hardware for-loop.  the same scalar register number is handed
 322   to every ALU.
 323
 324 * vector register numbers *DO* increase when allocated in the
 325   hardware for-loop.  sequentially-increasing register data
 326   is handed to sequential ALUs.
 327
 328 Vector Register Number Encoding
 329 ===============================
 330
 331 For the 48 bit format, when vs#/vd is 1, the actual 7-bit register number
 332 is derived from the corresponding 6-bit rs#/rd field:
 333
 334 +---------------------------------+
 335 | Actual 7-bit register number    |
 336 +===========+=============+=======+
 337 | Bit 6     | Bits 5:1    | Bit 0 |
 338 +-----------+-------------+-------+
 339 | rs#/rd[0] | rs#/rd[5:1] | 0     |
 340 +-----------+-------------+-------+
 341
 342 For the 64 bit format, the 7 bit register is constructed from the 7 bit
 343 fields: bits 0 to 4 from the 32 bit RV Standard format, bit 5 from the 48
 344 bit prefix and bit 6 from the 64 bit prefix.  Thus in the 64 bit format
 345 the full range of up to 128 registers is directly available. This for
 346 both when either scalar or vector mode is set.
 347
 348 Load/Store Kind (lsk) Field Encoding
 349 ====================================
 350
 351 +--------+-----+--------------------------------------------------------------------------------+
 352 | vd/vs2 | vs1 | Meaning                                                                        |
 353 +========+=====+================================================================================+
 354 | 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                       |
 355 +--------+-----+--------------------------------------------------------------------------------+
 356 | 1      | 0   | srcbase is scalar, LD/ST is unit strided                                       |
 357 +--------+-----+--------------------------------------------------------------------------------+
 358 | 0      | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
 359 +--------+-----+--------------------------------------------------------------------------------+
 360 | 1      | 1   | srcbase is a vector, LD/ST is a full vector LD/ST.                             |
 361 +--------+-----+--------------------------------------------------------------------------------+
 362
 363 Notes:
 364
 365 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2,
 366   predicate 1, predicate 2 and the stride register.
 367 * Complex strides may all be done with a general purpose vector of srcbases.
 368 * Twin predication may be used even when vd/vs1 is a scalar, to give
 369   VSPLAT and VSELECT, because the hardware loop ends on the first occurrence
 370   of a 1 in the predicate when a predicate is applied to a scalar.
 371 * Full vectorised gather/scatter is enabled when both registers are
 372   marked as vectorised, however unlike e.g Intel AVX512, twin predication
 373   can be applied.
 374
 375 Open question: RVV overloads the width field of LOAD-FP/STORE-FP
 376 using the bit 2 to indicate additional interpretation of the 11 bit
 377 immediate. Should this be considered?
 378
 379
 380 Sub-Vector Length (svlen) Field Encoding
 381 ========================================
 382
 383 NOTE: svlen is not the same as the main spec SUBVL.  When nondefault (not zero) SVPSTATE context is used for Sub vector loops. However is svlen is zero, STATE and SUBVL is used instead.
 384
 385 Bitwidth, from VL's perspective, is a multiple of the elwidth times svlen.
 386 So within each loop of VL there are svlen sub-elements of elwidth in size,
 387 just like in a SIMD architecture. When svlen is set to 0b00 (indicating
 388 svlen=1) no such SIMD-like behaviour exists and the subvectoring is
 389 disabled.
 390
 391 Predicate bits do not apply to the individual sub-vector elements, they
 392 apply to the entire subvector group. This saves instructions on setup
 393 of the predicate.
 394
 395 +----------------+-------+
 396 | svlen Encoding | Value |
 397 +================+=======+
 398 | 00             | SUBVL |
 399 +----------------+-------+
 400 | 01             | 2     |
 401 +----------------+-------+
 402 | 10             | 3     |
 403 +----------------+-------+
 404 | 11             | 4     |
 405 +----------------+-------+
 406
 407 In independent standalone implementations that do not implement the
 408 main specification, the value of SUBVL in the above table (svtyp=0b00)
 409 is set to 1, such that svlen is also 1.
 410
 411 Behaviour of operations that set svlen are identical to those of the
 412 main spec. See section on VLtyp, above.
 413
 414 Predication (pred) Field Encoding
 415 =================================
 416
 417 +------+------------+--------------------+----------------------------------------+
 418 | pred | Mnemonic   | Predicate Register | Meaning                                |
 419 +======+============+====================+========================================+
 420 | 000  | *None*     | *None*             | The instruction is unpredicated        |
 421 +------+------------+--------------------+----------------------------------------+
 422 | 001  | *Reserved* | *Reserved*         |                                        |
 423 +------+------------+--------------------+----------------------------------------+
 424 | 010  | !x9        | x9 (s1)            | execute vector op[0..i] on x9[i] == 0  |
 425 +------+------------+                    +----------------------------------------+
 426 | 011  | x9         |                    | execute vector op[0..i] on x9[i] == 1  |
 427 +------+------------+--------------------+----------------------------------------+
 428 | 100  | !x10       | x10 (a0)           | execute vector op[0..i] on x10[i] == 0 |
 429 +------+------------+                    +----------------------------------------+
 430 | 101  | x10        |                    | execute vector op[0..i] on x10[i] == 1 |
 431 +------+------------+--------------------+----------------------------------------+
 432 | 110  | !x11       | x11 (a1)           | execute vector op[0..i] on x11[i] == 0 |
 433 +------+------------+                    +----------------------------------------+
 434 | 111  | x11        |                    | execute vector op[0..i] on x11[i] == 1 |
 435 +------+------------+--------------------+----------------------------------------+
 436
 437 Twin-predication (tpred) Field Encoding
 438 =======================================
 439
 440 Twin-predication (ability to associate two predicate registers with an
 441 instruction) applies to MV, FCLASS, LD and ST.  The same format also
 442 applies to integer-branch-compare operations although it is **not** to be
 443 considered "twin" predication.  In the case of integer-branch-compare
 444 operations, the second register (if enabled) stores the results of the
 445 element comparisons.  See Appendix_ for details.
 446
 447 +-------+------------+--------------------+----------------------------------------------+
 448 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 449 +=======+============+====================+==============================================+
 450 | 000   | *None*     | *None*             | The instruction is unpredicated              |
 451 +-------+------------+--------------------+----------------------------------------------+
 452 | 001   | x9,off     | src=x9, dest=none  | src[0..i] uses x9[i], dest unpredicated      |
 453 +-------+------------+                    +----------------------------------------------+
 454 | 010   | off,x10    | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated     |
 455 +-------+------------+                    +----------------------------------------------+
 456 | 011   | x9,10      | src=x9, dest=x10   | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
 457 +-------+------------+--------------------+----------------------------------------------+
 458 | 100   | *None*     | *RESERVED*         | Instruction is unpredicated (TBD)            |
 459 +-------+------------+--------------------+----------------------------------------------+
 460 | 101   | !x9,off    | src=!x9, dest=none |                                              |
 461 +-------+------------+                    +----------------------------------------------+
 462 | 110   | off,!x10   | src=none, dest=!x10|                                              |
 463 +-------+------------+                    +----------------------------------------------+
 464 | 111   | !x9,!x10   | src=!x9, dest=!x10 |                                              |
 465 +-------+------------+--------------------+----------------------------------------------+
 466
 467 Integer Element Type (itype) Field Encoding
 468 ===========================================
 469
 470 +------------+-------+--------------+--------------+-----------------+-------------------+
 471 | Signedness | itype | Element Type | Mnemonic in  | Mnemonic in FP  | Meaning (INT may  |
 472 | [#sgn_def]_|       |              | Integer      | Instructions    | be un/signed, FP  |
 473 | [#sgn_def]_|       |              | Instructions | (such as fmv.x) | just re-sized     |
 474 +============+=======+==============+==============+=================+===================+
 475 | Unsigned   | 01    | u8           | BU           | BU              | Unsigned 8-bit    |
 476 |            +-------+--------------+--------------+-----------------+-------------------+
 477 |            | 10    | u16          | HU           | HU              | Unsigned 16-bit   |
 478 |            +-------+--------------+--------------+-----------------+-------------------+
 479 |            | 11    | u32          | WU           | WU              | Unsigned 32-bit   |
 480 |            +-------+--------------+--------------+-----------------+-------------------+
 481 |            | 00    | uXLEN        | WU/DU/QU     | WU/LU/TU        | Unsigned XLEN-bit |
 482 +------------+-------+--------------+--------------+-----------------+-------------------+
 483 | Signed     | 01    | i8           | BS           | BS              | Signed 8-bit      |
 484 |            +-------+--------------+--------------+-----------------+-------------------+
 485 |            | 10    | i16          | HS           | HS              | Signed 16-bit     |
 486 |            +-------+--------------+--------------+-----------------+-------------------+
 487 |            | 11    | i32          | W            | W               | Signed 32-bit     |
 488 |            +-------+--------------+--------------+-----------------+-------------------+
 489 |            | 00    | iXLEN        | W/D/Q        | W/L/T           | Signed XLEN-bit   |
 490 +------------+-------+--------------+--------------+-----------------+-------------------+
 491
 492 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
 493
 494 Note: vector mode is effectively a type-cast of the register file
 495 as if it was a sequential array being typecast to typedef itype[]
 496 (c syntax).  The starting point of the "typecast" is the vector
 497 register rs#/rd.
 498
 499 Example: if itype=0b10 (u16), and rd is set to "vector", and
 500 VL is set to 4, the 64-bit register at rd is subdivided into
 501 *FOUR* 16-bit destination elements.  It is *NOT* four
 502 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
 503 that are sign-extended from the source width size out to 64-bit,
 504 because that is itype=0b00 (uXLEN).
 505
 506 Note also: changing elwidth creates packed elements that, depending on
 507 VL, may create vectors that do not fit perfectly onto XLEN sized registry
 508 file bit-boundaries. This does NOT result in the destruction of the MSBs
 509 of the last register written to at the end of a VL loop. More details
 510 on how to handle this are described in the main Specification_.
 511
 512 Signedness Decision Procedure
 513 =============================
 514
 515 1. If the opcode field is either OP or OP-IMM, then
 516     1. Signedness is Unsigned.
 517 2. If the opcode field is either OP-32 or OP-IMM-32, then
 518     1. Signedness is Signed.
 519 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
 520     1. Signedness uses the encoded value.
 521 4. Otherwise,
 522     1. Signedness is Unsigned.
 523
 524 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w,
 525                since there is no fmv.x.wu
 526
 527 Vector Type and Predication 5-bit (vtp5) Field Encoding
 528 =========================================================
 529
 530 In the following table, X denotes a wildcard that is 0 or 1 and can be
 531 a different value for every occurrence.
 532
 533 +-------+-----------+-----------+
 534 | vtp5  | pred      | svlen     |
 535 +=======+===========+===========+
 536 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
 537 +-------+           |           |
 538 | 01XXX |           |           |
 539 +-------+           |           |
 540 | 000XX |           |           |
 541 +-------+-----------+-----------+
 542 | 001XX | *Reserved*            |
 543 +-------+-----------------------+
 544
 545 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
 546 =================================================================
 547
 548 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 549 different value for every occurrence.
 550
 551 +--------+------------+---------+------------+------------+
 552 | vitp6  | itype      | pred[2] | pred[0:1]  | svlen      |
 553 +========+============+=========+============+============+
 554 | XX1XXX | vitp6[5:4] | 0       | vitp6[3:2] | vitp6[1:0] |
 555 +--------+            |         |            |            |
 556 | XX00XX |            |         |            |            |
 557 +--------+------------+---------+------------+------------+
 558 | XX01XX | *Reserved*                                     |
 559 +--------+------------------------------------------------+
 560
 561 vitp7 field: only tpred
 562
 563 +---------+------------+----------+-------------+------------+
 564 | vitp7   | itype      | tpred[2] | tpred[0:1]  | svlen      |
 565 +=========+============+==========+=============+============+
 566 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2]  | vitp7[1:0] |
 567 +---------+------------+----------+-------------+------------+
 568
 569 48-bit Instruction Encoding Decision Procedure
 570 ==============================================
 571
 572 In the following decision procedure, *Reserved* means that there is not
 573 yet a defined 48-bit instruction encoding for the base instruction.
 574
 575 1. If the base instruction is a load instruction, then
 576     a. If the base instruction is an I-type instruction, then
 577         1. The encoding is P48-LD-type.
 578     b. Otherwise
 579         1. The encoding is *Reserved*.
 580 2. If the base instruction is a store instruction, then
 581     a. If the base instruction is an S-type instruction, then
 582         1. The encoding is P48-ST-type.
 583     b. Otherwise
 584         1. The encoding is *Reserved*.
 585 3. If the base instruction is a SYSTEM instruction, then
 586     a. The encoding is *Reserved*.
 587 4. If the base instruction is an integer instruction, then
 588     a. If the base instruction is an R-type instruction, then
 589         1. The encoding is P48-R-type.
 590     b. If the base instruction is an I-type instruction, then
 591         1. The encoding is P48-I-type.
 592     c. If the base instruction is an S-type instruction, then
 593         1. The encoding is *Reserved*.
 594     d. If the base instruction is an B-type instruction, then
 595         1. The encoding is *Reserved*.
 596     e. If the base instruction is an U-type instruction, then
 597         1. The encoding is P48-U-type.
 598     f. If the base instruction is an J-type instruction, then
 599         1. The encoding is *Reserved*.
 600     g. Otherwise
 601         1. The encoding is *Reserved*.
 602 5. If the base instruction is a floating-point instruction, then
 603     a. If the base instruction is an R-type instruction, then
 604         1. The encoding is P48-FR-type.
 605     b. If the base instruction is an I-type instruction, then
 606         1. The encoding is P48-FI-type.
 607     c. If the base instruction is an S-type instruction, then
 608         1. The encoding is *Reserved*.
 609     d. If the base instruction is an B-type instruction, then
 610         1. The encoding is *Reserved*.
 611     e. If the base instruction is an U-type instruction, then
 612         1. The encoding is *Reserved*.
 613     f. If the base instruction is an J-type instruction, then
 614         1. The encoding is *Reserved*.
 615     g. If the base instruction is an R4-type instruction, then
 616         1. The encoding is P48-FR4-type.
 617     h. Otherwise
 618         1. The encoding is *Reserved*.
 619 6. Otherwise
 620     a. The encoding is *Reserved*.
 621
 622 CSR Registers
 623 =============
 624
 625 CSRs are the same as in the main Specification_, if associated
 626 functionality is implemented. They have the exact same meaning as in
 627 the main specification.
 628
 629 * VL
 630 * MVL
 631 * SVPSTATE
 632 * SUBVL
 633
 634 Associated SET and GET on the CSRs is exactly as in the main spec as well
 635 (including CSRRWI and CSRRW differences).
 636
 637 Note that if both VLtyp and svlen are not implemented, SVPSTATE is not required. Also if VL and SUBVL are not implemented, STATE from the main Specification_ is not required either.
 638
 639 However if partial functionality is implemented, the unimplemented bits
 640 in STATE and SVPSTATE must be zero, and, in the UNIX Platform, an illegal exception
 641 **MUST** be raised if unsupported bits are written to.
 642
 643 SVPSTATE fields are exactly the same layout as STATE:
 644
 645 +----------+----------+----------+----------+----------+---------+---------+
 646 | (31..28) | (27..26) | (25..24) | (23..18) | (17..12) | (11..6) | (5...0) |
 647 +----------+----------+----------+----------+----------+---------+---------+
 648 | rsvd     | dsvoffs  | subvl    | destoffs | srcoffs  | vl      | maxvl   |
 649 +----------+----------+----------+----------+----------+---------+---------+
 650
 651 However note that where STATE stores the scalar register number to be used as VL, SVPSTATE.VL actually contains the actual VL value, in an identical fashion to RVV.
 652
 653 Additional Instructions
 654 =======================
 655
 656 * Add instructions to convert between integer types.
 657 * Add instructions to `swizzle`_ elements in sub-vectors. Note that
 658   the sub-vector lengths of the source and destination won't necessarily
 659   match.
 660 * Add instructions to transpose (2-4)x(2-4) element matrices.
 661 * Add instructions to insert or extract a sub-vector from a vector, with
 662   the index allowed to be both immediate and from a register (*immediate
 663   can be covered by twin-predication, register might be, by virtue of
 664   predicates being registers*)
 665 * Add a register gather instruction (aka MV.X: regfile[rd] =
 666   regfile[regfile[rs1]])
 667
 668 subelement swizzle example:
 669
 670     velswizzle x32, x64, SRCSUBVL=3, DESTSUBVL=4, ELTYPE=u8, elements=[0, 0, 2, 1]
 671
 672 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
 673
 674 questions
 675 =========
 676
 677 Moved to the discussion page (link at top of this page)
 678
 679 TODO
 680 ====
 681
 682 Work out a way to do sub-element swizzling.
 683