add interrupt handling section

diff --git a/interrupts/interrupt_handling.mdwn b/interrupts/interrupt_handling.mdwn
index a0907bbf68249da79a113509c95927b7c6b7d97a..57cfed24da5a8b7590382bb4fe43e59e5dfb3d0f 100644 (file)
--- a/interrupts/interrupt_handling.mdwn
+++ b/interrupts/interrupt_handling.mdwn
@@ -15,17 +15,20 @@ familiar with markdown or editing of wikis please contact
 luke.leighton@gmail.com, sending the appropriate text, for inclusion here.
 
 * **Libre-RISCV Shakti M-Class**: a 300-400 pin SoC with almost a hundred
 luke.leighton@gmail.com, sending the appropriate text, for inclusion here.
 
 * **Libre-RISCV Shakti M-Class**: a 300-400 pin SoC with almost a hundred

-  separate and distinct "slow" (below 160mhz) peripherals that need nothing
-  particularly special in the way of fast latency IRQs, just lots of them.
-  Five UARTs, each requiring one IRQ line; Four I2C peripherals, each
-  requiring two IRQ lines, Multiple Quad SPI interfaces requring **six**
-  IRQ lines (each!), the number of IRQ lines required to cover such
-  a significant number of peripherals begins to add up quite rapidly.
-  However despite this, the PLIC as it stands (privspec-v-1.10 chapter 7)
-  actually covers the requirements quite nicely, as long as it can cope
-  with large numbers *of* IRQ lines (which it can).  Thus the Shakti
-  PLIC Peripheral code has been modified from its original (which could
-  handle up to XLEN separate lines) to a hierarchical arrangement that
-  can handle up to 1024 separate and distinct IRQs
+  separate and distinct "slow" (below 160mhz) peripherals that need
+  nothing particularly special in the way of fast latency IRQs, just lots
+  of them.  Five UARTs, each requiring one IRQ line; Four I2C peripherals,
+  each requiring two IRQ lines, Multiple Quad SPI interfaces requring
+  **six** IRQ lines (each!), and 32 "EINT" lines (general-purpose
+  external interrupt) which are intended for mundane purposes such as
+  "lid opened", or "volume key pressed" and "headphone jack inserted",
+  the number of IRQ lines required to cover such a significant number
+  of peripherals begins to add up quite rapidly.  However despite this,
+  the PLIC as it stands (privspec-v-1.10 chapter 7) actually covers the
+  requirements quite nicely, as long as it can cope with large numbers
+  *of* IRQ lines (which it can).  Thus the Shakti PLIC Peripheral code
+  has been modified from its original (which could handle up to XLEN
+  separate lines) to a hierarchical arrangement that can handle up to
+  1024 separate and distinct IRQs

   <http://git.libre-riscv.org/?p=shakti-peripherals.git;a=blob;f=src/peripherals/plic/plic.bsv>
 
   <http://git.libre-riscv.org/?p=shakti-peripherals.git;a=blob;f=src/peripherals/plic/plic.bsv>