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add ddr3 ohwr link
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 28 Jun 2018 17:45:11 +0000 (18:45 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 28 Jun 2018 17:45:11 +0000 (18:45 +0100)
shakti/m_class/DDR.mdwn patch | blob | history

diff --git a/shakti/m_class/DDR.mdwn b/shakti/m_class/DDR.mdwn
index 8bae234cc3bff39075673eb10ca6cdbbb57074e6..8607cddf11f0222e6a7dbf4e628f1e8e51691c27 100644 (file)
--- a/shakti/m_class/DDR.mdwn
+++ b/shakti/m_class/DDR.mdwn
@@ -1,3 +1,4 @@
 # DDR (DRAM) Controller and PHY
 
 * <https://github.com/enjoy-digital/litedram> - controller inc. DDR3 / LPDDR3
+* <https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki> - CERN DDR3 ctrl
http://libre-riscv.org ikiwiki