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add ddr3 ohwr link
[libreriscv.git] / shakti / m_class / DDR.mdwn
1 # DDR (DRAM) Controller and PHY
2
3 * <https://github.com/enjoy-digital/litedram> - controller inc. DDR3 / LPDDR3
4 * <https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki> - CERN DDR3 ctrl
http://libre-riscv.org ikiwiki