(no commit message)
authorcolepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Sun, 1 Nov 2020 22:26:23 +0000 (22:26 +0000)
committerIkiWiki <ikiwiki.info>
Sun, 1 Nov 2020 22:26:23 +0000 (22:26 +0000)
HDL_workflow/fpga.mdwn

index d62fe95e5f98f6ed5dab9e928b24c422b6d95618..5ff231436a67d59d523e9c9f1785b89457b1327b 100644 (file)
@@ -54,7 +54,11 @@ lkcl:
 
 ## Connecting the dots:
 
-litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
+Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
+
+STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
+
+Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 
     ("gpio", 0,
         Subsignal"p", Pins("B11")),