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added minerva and chips4makers jtag
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 8 May 2020 22:12:53 +0000 (23:12 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 8 May 2020 22:12:53 +0000 (23:12 +0100)
shakti/m_class/JTAG.mdwn patch | blob | history

diff --git a/shakti/m_class/JTAG.mdwn b/shakti/m_class/JTAG.mdwn
index 6a75bd016e0dfde1ba1ba879517e7349e27af95f..7d88d3d6305008dcb6a96aed88b13fc0556cd509 100644 (file)
--- a/shakti/m_class/JTAG.mdwn
+++ b/shakti/m_class/JTAG.mdwn
@@ -1,4 +1,6 @@
 # JTAG
 
+* <https://gitlab.com/Chips4Makers/c4m-jtag> nmigen JTAG
+* <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/units/debug/controller.py;h=7304303e577b14eebba15144642eb7bee829e107;hb=a54adcb65bad37b398b11e33a824c7d08c5fe509> minerva nmigen JTAG
 * <http://processors.wiki.ti.com/index.php/JTAG_(MSP430)#4_Wire_JTAG>
 
http://libre-riscv.org ikiwiki