core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         HAS_BTC : boolean := true;
  16         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  17         LOG_LENGTH : natural := 512;
  18         ICACHE_NUM_LINES : natural := 64;
  19         ICACHE_NUM_WAYS : natural := 2;
  20         ICACHE_TLB_SIZE : natural := 64;
  21         DCACHE_NUM_LINES : natural := 64;
  22         DCACHE_NUM_WAYS : natural := 2;
  23         DCACHE_TLB_SET_SIZE : natural := 64;
  24         DCACHE_TLB_NUM_WAYS : natural := 2
  25         );
  26     port (
  27         clk          : in std_ulogic;
  28         rst          : in std_ulogic;
  29
  30         -- Alternate reset (0xffff0000) for use by DRAM init fw
  31         alt_reset    : in std_ulogic;
  32
  33         -- Wishbone interface
  34         wishbone_insn_in  : in wishbone_slave_out;
  35         wishbone_insn_out : out wishbone_master_out;
  36
  37         wishbone_data_in  : in wishbone_slave_out;
  38         wishbone_data_out : out wishbone_master_out;
  39
  40         dmi_addr        : in std_ulogic_vector(3 downto 0);
  41         dmi_din         : in std_ulogic_vector(63 downto 0);
  42         dmi_dout        : out std_ulogic_vector(63 downto 0);
  43         dmi_req         : in std_ulogic;
  44         dmi_wr          : in std_ulogic;
  45         dmi_ack         : out std_ulogic;
  46
  47         ext_irq         : in std_ulogic;
  48
  49         terminated_out   : out std_logic
  50         );
  51 end core;
  52
  53 architecture behave of core is
  54     -- icache signals
  55     signal fetch1_to_icache : Fetch1ToIcacheType;
  56     signal writeback_to_fetch1: WritebackToFetch1Type;
  57     signal icache_to_decode1 : IcacheToDecode1Type;
  58     signal mmu_to_icache : MmuToIcacheType;
  59
  60     -- decode signals
  61     signal decode1_to_decode2: Decode1ToDecode2Type;
  62     signal decode1_to_fetch1: Decode1ToFetch1Type;
  63     signal decode2_to_execute1: Decode2ToExecute1Type;
  64
  65     -- register file signals
  66     signal register_file_to_decode2: RegisterFileToDecode2Type;
  67     signal decode2_to_register_file: Decode2ToRegisterFileType;
  68     signal writeback_to_register_file: WritebackToRegisterFileType;
  69
  70     -- CR file signals
  71     signal decode2_to_cr_file: Decode2ToCrFileType;
  72     signal cr_file_to_decode2: CrFileToDecode2Type;
  73     signal writeback_to_cr_file: WritebackToCrFileType;
  74
  75     -- execute signals
  76     signal execute1_to_writeback: Execute1ToWritebackType;
  77     signal execute1_bypass: bypass_data_t;
  78     signal execute1_cr_bypass: cr_bypass_data_t;
  79
  80     -- load store signals
  81     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  82     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  83     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  84     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  85     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  86
  87     -- dcache signals
  88     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  89     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  90     signal mmu_to_dcache: MmuToDcacheType;
  91     signal dcache_to_mmu: DcacheToMmuType;
  92
  93     -- FPU signals
  94     signal execute1_to_fpu: Execute1ToFPUType;
  95     signal fpu_to_execute1: FPUToExecute1Type;
  96     signal fpu_to_writeback: FPUToWritebackType;
  97
  98     -- local signals
  99     signal fetch1_stall_in : std_ulogic;
 100     signal icache_stall_out : std_ulogic;
 101     signal icache_stall_in : std_ulogic;
 102     signal decode1_stall_in : std_ulogic;
 103     signal decode1_busy     : std_ulogic;
 104     signal decode2_busy_in : std_ulogic;
 105     signal decode2_stall_out : std_ulogic;
 106     signal ex1_icache_inval: std_ulogic;
 107     signal ex1_busy_out: std_ulogic;
 108     signal dcache_stall_out: std_ulogic;
 109
 110     signal flush: std_ulogic;
 111     signal decode1_flush: std_ulogic;
 112     signal fetch1_flush: std_ulogic;
 113
 114     signal complete: instr_tag_t;
 115     signal terminate: std_ulogic;
 116     signal core_rst: std_ulogic;
 117     signal icache_inv: std_ulogic;
 118     signal do_interrupt: std_ulogic;
 119
 120     -- Delayed/Latched resets and alt_reset
 121     signal rst_fetch1  : std_ulogic := '1';
 122     signal rst_fetch2  : std_ulogic := '1';
 123     signal rst_icache  : std_ulogic := '1';
 124     signal rst_dcache  : std_ulogic := '1';
 125     signal rst_dec1    : std_ulogic := '1';
 126     signal rst_dec2    : std_ulogic := '1';
 127     signal rst_ex1     : std_ulogic := '1';
 128     signal rst_fpu     : std_ulogic := '1';
 129     signal rst_ls1     : std_ulogic := '1';
 130     signal rst_wback   : std_ulogic := '1';
 131     signal rst_dbg     : std_ulogic := '1';
 132     signal alt_reset_d : std_ulogic;
 133
 134     signal sim_cr_dump: std_ulogic;
 135
 136     -- Debug actions
 137     signal dbg_core_stop: std_ulogic;
 138     signal dbg_core_rst: std_ulogic;
 139     signal dbg_icache_rst: std_ulogic;
 140
 141     signal dbg_gpr_req : std_ulogic;
 142     signal dbg_gpr_ack : std_ulogic;
 143     signal dbg_gpr_addr : gspr_index_t;
 144     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 145
 146     signal msr : std_ulogic_vector(63 downto 0);
 147
 148     -- Debug status
 149     signal dbg_core_is_stopped: std_ulogic;
 150
 151     -- Logging signals
 152     signal log_data    : std_ulogic_vector(255 downto 0);
 153     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 154     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 155     signal log_rd_data : std_ulogic_vector(63 downto 0);
 156
 157     function keep_h(disable : boolean) return string is
 158     begin
 159         if disable then
 160             return "yes";
 161         else
 162             return "no";
 163         end if;
 164     end function;
 165     attribute keep_hierarchy : string;
 166     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 167     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 168     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 169     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 170     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 171     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 172     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 173     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 174     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 175     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 176     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 177     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 178 begin
 179
 180     core_rst <= dbg_core_rst or rst;
 181
 182     resets: process(clk)
 183     begin
 184         if rising_edge(clk) then
 185             rst_fetch1  <= core_rst;
 186             rst_fetch2  <= core_rst;
 187             rst_icache  <= core_rst;
 188             rst_dcache  <= core_rst;
 189             rst_dec1    <= core_rst;
 190             rst_dec2    <= core_rst;
 191             rst_ex1     <= core_rst;
 192             rst_fpu     <= core_rst;
 193             rst_ls1     <= core_rst;
 194             rst_wback   <= core_rst;
 195             rst_dbg     <= rst;
 196             alt_reset_d <= alt_reset;
 197         end if;
 198     end process;
 199
 200     fetch1_0: entity work.fetch1
 201         generic map (
 202             RESET_ADDRESS => (others => '0'),
 203             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 204             HAS_BTC => HAS_BTC
 205             )
 206         port map (
 207             clk => clk,
 208             rst => rst_fetch1,
 209             alt_reset_in => alt_reset_d,
 210             stall_in => fetch1_stall_in,
 211             flush_in => fetch1_flush,
 212             inval_btc => ex1_icache_inval or mmu_to_icache.tlbie,
 213             stop_in => dbg_core_stop,
 214             d_in => decode1_to_fetch1,
 215             w_in => writeback_to_fetch1,
 216             i_out => fetch1_to_icache,
 217             log_out => log_data(42 downto 0)
 218             );
 219
 220     fetch1_stall_in <= icache_stall_out or decode1_busy;
 221     fetch1_flush <= flush or decode1_flush;
 222
 223     icache_0: entity work.icache
 224         generic map(
 225             SIM => SIM,
 226             LINE_SIZE => 64,
 227             NUM_LINES => ICACHE_NUM_LINES,
 228             NUM_WAYS => ICACHE_NUM_WAYS,
 229             TLB_SIZE => ICACHE_TLB_SIZE,
 230             LOG_LENGTH => LOG_LENGTH
 231             )
 232         port map(
 233             clk => clk,
 234             rst => rst_icache,
 235             i_in => fetch1_to_icache,
 236             i_out => icache_to_decode1,
 237             m_in => mmu_to_icache,
 238             flush_in => fetch1_flush,
 239             inval_in => dbg_icache_rst or ex1_icache_inval,
 240             stall_in => icache_stall_in,
 241             stall_out => icache_stall_out,
 242             wishbone_out => wishbone_insn_out,
 243             wishbone_in => wishbone_insn_in,
 244             log_out => log_data(96 downto 43)
 245             );
 246
 247     icache_stall_in <= decode1_busy;
 248
 249     decode1_0: entity work.decode1
 250         generic map(
 251             HAS_FPU => HAS_FPU,
 252             LOG_LENGTH => LOG_LENGTH
 253             )
 254         port map (
 255             clk => clk,
 256             rst => rst_dec1,
 257             stall_in => decode1_stall_in,
 258             flush_in => flush,
 259             flush_out => decode1_flush,
 260             busy_out => decode1_busy,
 261             f_in => icache_to_decode1,
 262             d_out => decode1_to_decode2,
 263             f_out => decode1_to_fetch1,
 264             log_out => log_data(109 downto 97)
 265             );
 266
 267     decode1_stall_in <= decode2_stall_out;
 268
 269     decode2_0: entity work.decode2
 270         generic map (
 271             EX1_BYPASS => EX1_BYPASS,
 272             HAS_FPU => HAS_FPU,
 273             LOG_LENGTH => LOG_LENGTH
 274             )
 275         port map (
 276             clk => clk,
 277             rst => rst_dec2,
 278             busy_in => decode2_busy_in,
 279             stall_out => decode2_stall_out,
 280             flush_in => flush,
 281             complete_in => complete,
 282             stopped_out => dbg_core_is_stopped,
 283             d_in => decode1_to_decode2,
 284             e_out => decode2_to_execute1,
 285             r_in => register_file_to_decode2,
 286             r_out => decode2_to_register_file,
 287             c_in => cr_file_to_decode2,
 288             c_out => decode2_to_cr_file,
 289             execute_bypass => execute1_bypass,
 290             execute_cr_bypass => execute1_cr_bypass,
 291             log_out => log_data(119 downto 110)
 292             );
 293     decode2_busy_in <= ex1_busy_out;
 294
 295     register_file_0: entity work.register_file
 296         generic map (
 297             SIM => SIM,
 298             HAS_FPU => HAS_FPU,
 299             LOG_LENGTH => LOG_LENGTH
 300             )
 301         port map (
 302             clk => clk,
 303             d_in => decode2_to_register_file,
 304             d_out => register_file_to_decode2,
 305             w_in => writeback_to_register_file,
 306             dbg_gpr_req => dbg_gpr_req,
 307             dbg_gpr_ack => dbg_gpr_ack,
 308             dbg_gpr_addr => dbg_gpr_addr,
 309             dbg_gpr_data => dbg_gpr_data,
 310             sim_dump => terminate,
 311             sim_dump_done => sim_cr_dump,
 312             log_out => log_data(255 downto 184)
 313             );
 314
 315     cr_file_0: entity work.cr_file
 316         generic map (
 317             SIM => SIM,
 318             LOG_LENGTH => LOG_LENGTH
 319             )
 320         port map (
 321             clk => clk,
 322             d_in => decode2_to_cr_file,
 323             d_out => cr_file_to_decode2,
 324             w_in => writeback_to_cr_file,
 325             sim_dump => sim_cr_dump,
 326             log_out => log_data(183 downto 171)
 327             );
 328
 329     execute1_0: entity work.execute1
 330         generic map (
 331             EX1_BYPASS => EX1_BYPASS,
 332             HAS_FPU => HAS_FPU,
 333             LOG_LENGTH => LOG_LENGTH
 334             )
 335         port map (
 336             clk => clk,
 337             rst => rst_ex1,
 338             flush_in => flush,
 339             busy_out => ex1_busy_out,
 340             e_in => decode2_to_execute1,
 341             l_in => loadstore1_to_execute1,
 342             fp_in => fpu_to_execute1,
 343             ext_irq_in => ext_irq,
 344             interrupt_in => do_interrupt,
 345             l_out => execute1_to_loadstore1,
 346             fp_out => execute1_to_fpu,
 347             e_out => execute1_to_writeback,
 348             bypass_data => execute1_bypass,
 349             bypass_cr_data => execute1_cr_bypass,
 350             icache_inval => ex1_icache_inval,
 351             dbg_msr_out => msr,
 352             terminate_out => terminate,
 353             log_out => log_data(134 downto 120),
 354             log_rd_addr => log_rd_addr,
 355             log_rd_data => log_rd_data,
 356             log_wr_addr => log_wr_addr
 357             );
 358
 359     with_fpu: if HAS_FPU generate
 360     begin
 361         fpu_0: entity work.fpu
 362             port map (
 363                 clk => clk,
 364                 rst => rst_fpu,
 365                 e_in => execute1_to_fpu,
 366                 e_out => fpu_to_execute1,
 367                 w_out => fpu_to_writeback
 368                 );
 369     end generate;
 370
 371     no_fpu: if not HAS_FPU generate
 372     begin
 373         fpu_to_execute1 <= FPUToExecute1Init;
 374         fpu_to_writeback <= FPUToWritebackInit;
 375     end generate;
 376
 377     loadstore1_0: entity work.loadstore1
 378         generic map (
 379             HAS_FPU => HAS_FPU,
 380             LOG_LENGTH => LOG_LENGTH
 381             )
 382         port map (
 383             clk => clk,
 384             rst => rst_ls1,
 385             l_in => execute1_to_loadstore1,
 386             e_out => loadstore1_to_execute1,
 387             l_out => loadstore1_to_writeback,
 388             d_out => loadstore1_to_dcache,
 389             d_in => dcache_to_loadstore1,
 390             m_out => loadstore1_to_mmu,
 391             m_in => mmu_to_loadstore1,
 392             dc_stall => dcache_stall_out,
 393             log_out => log_data(149 downto 140)
 394             );
 395
 396     mmu_0: entity work.mmu
 397         port map (
 398             clk => clk,
 399             rst => core_rst,
 400             l_in => loadstore1_to_mmu,
 401             l_out => mmu_to_loadstore1,
 402             d_out => mmu_to_dcache,
 403             d_in => dcache_to_mmu,
 404             i_out => mmu_to_icache
 405             );
 406
 407     dcache_0: entity work.dcache
 408         generic map(
 409             LINE_SIZE => 64,
 410             NUM_LINES => DCACHE_NUM_LINES,
 411             NUM_WAYS => DCACHE_NUM_WAYS,
 412             TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
 413             TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS,
 414             LOG_LENGTH => LOG_LENGTH
 415             )
 416         port map (
 417             clk => clk,
 418             rst => rst_dcache,
 419             d_in => loadstore1_to_dcache,
 420             d_out => dcache_to_loadstore1,
 421             m_in => mmu_to_dcache,
 422             m_out => dcache_to_mmu,
 423             stall_out => dcache_stall_out,
 424             wishbone_in => wishbone_data_in,
 425             wishbone_out => wishbone_data_out,
 426             log_out => log_data(170 downto 151)
 427             );
 428
 429     writeback_0: entity work.writeback
 430         port map (
 431             clk => clk,
 432             rst => rst_wback,
 433             flush_out => flush,
 434             e_in => execute1_to_writeback,
 435             l_in => loadstore1_to_writeback,
 436             fp_in => fpu_to_writeback,
 437             w_out => writeback_to_register_file,
 438             c_out => writeback_to_cr_file,
 439             f_out => writeback_to_fetch1,
 440             interrupt_out => do_interrupt,
 441             complete_out => complete
 442             );
 443
 444     log_data(150) <= '0';
 445     log_data(139 downto 135) <= "00000";
 446
 447     debug_0: entity work.core_debug
 448         generic map (
 449             LOG_LENGTH => LOG_LENGTH
 450             )
 451         port map (
 452             clk => clk,
 453             rst => rst_dbg,
 454             dmi_addr => dmi_addr,
 455             dmi_din => dmi_din,
 456             dmi_dout => dmi_dout,
 457             dmi_req => dmi_req,
 458             dmi_wr => dmi_wr,
 459             dmi_ack => dmi_ack,
 460             core_stop => dbg_core_stop,
 461             core_rst => dbg_core_rst,
 462             icache_rst => dbg_icache_rst,
 463             terminate => terminate,
 464             core_stopped => dbg_core_is_stopped,
 465             nia => fetch1_to_icache.nia,
 466             msr => msr,
 467             dbg_gpr_req => dbg_gpr_req,
 468             dbg_gpr_ack => dbg_gpr_ack,
 469             dbg_gpr_addr => dbg_gpr_addr,
 470             dbg_gpr_data => dbg_gpr_data,
 471             log_data => log_data,
 472             log_read_addr => log_rd_addr,
 473             log_read_data => log_rd_data,
 474             log_write_addr => log_wr_addr,
 475             terminated_out => terminated_out
 476             );
 477
 478 end behave;