core_dram_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8 use work.utils.all;
   9
  10 entity core_dram_tb is
  11     generic (
  12         MEMORY_SIZE    : natural := (384*1024);
  13         MAIN_RAM_FILE  : string  := "main_ram.bin";
  14         DRAM_INIT_FILE : string  := "";
  15         DRAM_INIT_SIZE : natural := 16#c000#
  16         );
  17 end core_dram_tb;
  18
  19 architecture behave of core_dram_tb is
  20     signal clk, rst: std_logic;
  21     signal system_clk, soc_rst : std_ulogic;
  22
  23     -- testbench signals
  24     constant clk_period : time := 10 ns;
  25
  26     -- Sim DRAM
  27     signal wb_dram_in : wishbone_master_out;
  28     signal wb_dram_out : wishbone_slave_out;
  29     signal wb_ext_io_in : wb_io_master_out;
  30     signal wb_ext_io_out : wb_io_slave_out;
  31     signal wb_ext_is_dram_csr : std_ulogic;
  32     signal wb_ext_is_dram_init : std_ulogic;
  33     signal core_alt_reset : std_ulogic;
  34
  35     -- SPI
  36     signal spi_sck     : std_ulogic;
  37     signal spi_cs_n    : std_ulogic := '1';
  38     signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
  39     signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
  40     signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
  41     signal fl_hold_n   : std_logic;
  42     signal fl_wp_n     : std_logic;
  43     signal fl_mosi     : std_logic;
  44     signal fl_miso     : std_logic;
  45
  46     -- ROM size
  47     function get_rom_size return natural is
  48     begin
  49         if MEMORY_SIZE = 0 then
  50             return DRAM_INIT_SIZE;
  51         else
  52             return 0;
  53         end if;
  54     end function;
  55
  56     constant ROM_SIZE : natural := get_rom_size;
  57 begin
  58
  59     soc0: entity work.soc
  60         generic map(
  61             SIM => true,
  62             MEMORY_SIZE => MEMORY_SIZE,
  63             RAM_INIT_FILE => MAIN_RAM_FILE,
  64             HAS_DRAM => true,
  65             DRAM_SIZE => 256 * 1024 * 1024,
  66             DRAM_INIT_SIZE => ROM_SIZE,
  67             CLK_FREQ => 100000000,
  68             HAS_SPI_FLASH    => true,
  69             SPI_FLASH_DLINES => 4,
  70             SPI_FLASH_OFFSET => 0
  71             )
  72         port map(
  73             rst => soc_rst,
  74             system_clk => system_clk,
  75             wb_dram_in => wb_dram_in,
  76             wb_dram_out => wb_dram_out,
  77             wb_ext_io_in => wb_ext_io_in,
  78             wb_ext_io_out => wb_ext_io_out,
  79             wb_ext_is_dram_csr => wb_ext_is_dram_csr,
  80             wb_ext_is_dram_init => wb_ext_is_dram_init,
  81             spi_flash_sck     => spi_sck,
  82             spi_flash_cs_n    => spi_cs_n,
  83             spi_flash_sdat_o  => spi_sdat_o,
  84             spi_flash_sdat_oe => spi_sdat_oe,
  85             spi_flash_sdat_i  => spi_sdat_i,
  86             alt_reset => core_alt_reset
  87             );
  88
  89         flash: entity work.s25fl128s
  90         generic map (
  91             TimingModel => "S25FL128SAGNFI000_R_30pF",
  92             LongTimming => false,
  93             tdevice_PU => 10 ns,
  94             tdevice_PP256 => 100 ns,
  95             tdevice_PP512 => 100 ns,
  96             tdevice_WRR   => 100 ns,
  97             UserPreload => TRUE
  98             )
  99         port map(
 100             SCK => spi_sck,
 101             SI => fl_mosi,
 102             CSNeg => spi_cs_n,
 103             HOLDNeg => fl_hold_n,
 104             WPNeg => fl_wp_n,
 105             RSTNeg => '1',
 106             SO => fl_miso
 107             );
 108
 109     fl_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
 110     fl_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
 111     fl_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
 112     fl_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else '1' when spi_sdat_oe(0) = '1' else 'Z';
 113
 114     spi_sdat_i(0) <= fl_mosi;
 115     spi_sdat_i(1) <= fl_miso;
 116     spi_sdat_i(2) <= fl_wp_n;
 117     spi_sdat_i(3) <= fl_hold_n;
 118
 119     dram: entity work.litedram_wrapper
 120         generic map(
 121             DRAM_ABITS => 24,
 122             DRAM_ALINES => 1,
 123             DRAM_DLINES => 16,
 124             DRAM_CKLINES => 1,
 125             DRAM_PORT_WIDTH => 128,
 126             PAYLOAD_FILE => DRAM_INIT_FILE,
 127             PAYLOAD_SIZE => ROM_SIZE
 128             )
 129         port map(
 130             clk_in          => clk,
 131             rst             => rst,
 132             system_clk      => system_clk,
 133             system_reset    => soc_rst,
 134             core_alt_reset  => core_alt_reset,
 135
 136             wb_in           => wb_dram_in,
 137             wb_out          => wb_dram_out,
 138             wb_ctrl_in      => wb_ext_io_in,
 139             wb_ctrl_out     => wb_ext_io_out,
 140             wb_ctrl_is_csr  => wb_ext_is_dram_csr,
 141             wb_ctrl_is_init => wb_ext_is_dram_init
 142             );
 143
 144     clk_process: process
 145     begin
 146         clk <= '0';
 147         wait for clk_period/2;
 148         clk <= '1';
 149         wait for clk_period/2;
 150     end process;
 151
 152     rst_process: process
 153     begin
 154         rst <= '1';
 155         wait for 10*clk_period;
 156         rst <= '0';
 157         wait;
 158     end process;
 159
 160     jtag: entity work.sim_jtag;
 161
 162 end;