core_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core_tb is
  10 end core_tb;
  11
  12 architecture behave of core_tb is
  13         signal clk, rst: std_logic;
  14
  15         -- testbench signals
  16         constant clk_period : time := 10 ns;
  17 begin
  18
  19     soc0: entity work.soc
  20         generic map(
  21             SIM => true,
  22             MEMORY_SIZE => (384*1024),
  23             RAM_INIT_FILE => "main_ram.bin",
  24             CLK_FREQ => 100000000
  25             )
  26         port map(
  27             rst => rst,
  28             system_clk => clk
  29             );
  30
  31     clk_process: process
  32     begin
  33         clk <= '0';
  34         wait for clk_period/2;
  35         clk <= '1';
  36         wait for clk_period/2;
  37     end process;
  38
  39     rst_process: process
  40     begin
  41         rst <= '1';
  42         wait for 10*clk_period;
  43         rst <= '0';
  44         wait;
  45     end process;
  46
  47     jtag: entity work.sim_jtag;
  48
  49 end;