microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - control.vhdl
  23       - execute1.vhdl
  24       - fpu.vhdl
  25       - loadstore1.vhdl
  26       - mmu.vhdl
  27       - dcache.vhdl
  28       - divider.vhdl
  29       - rotator.vhdl
  30       - writeback.vhdl
  31       - insn_helpers.vhdl
  32       - core.vhdl
  33       - icache.vhdl
  34       - plru.vhdl
  35       - cache_ram.vhdl
  36       - core_debug.vhdl
  37       - utils.vhdl
  38     file_type : vhdlSource-2008
  39
  40   soc:
  41     files:
  42       - wishbone_arbiter.vhdl
  43       - wishbone_debug_master.vhdl
  44       - wishbone_bram_wrapper.vhdl
  45       - soc.vhdl
  46       - xics.vhdl
  47       - syscon.vhdl
  48       - sync_fifo.vhdl
  49       - spi_rxtx.vhdl
  50       - spi_flash_ctrl.vhdl
  51     file_type : vhdlSource-2008
  52
  53   fpga:
  54     files:
  55       - fpga/main_bram.vhdl
  56       - fpga/soc_reset.vhdl
  57       - fpga/pp_fifo.vhd
  58       - fpga/pp_soc_uart.vhd
  59       - fpga/pp_utilities.vhd
  60       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  61     file_type : vhdlSource-2008
  62
  63   xilinx_specific:
  64     files:
  65       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  66       - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
  67       - fpga/fpga-random.xdc : {file_type : xdc}
  68
  69   debug_xilinx:
  70     files:
  71       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  72
  73   debug_dummy:
  74     files:
  75       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  76
  77   nexys_a7:
  78     files:
  79       - fpga/nexys_a7.xdc : {file_type : xdc}
  80       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  81       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  82
  83   nexys_video:
  84     files:
  85       - fpga/nexys-video.xdc : {file_type : xdc}
  86       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  87       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  88
  89   acorn_cle_215:
  90     files:
  91       - fpga/acorn-cle-215.xdc : {file_type : xdc}
  92       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  93       - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
  94
  95   genesys2:
  96     files:
  97       - fpga/genesys2.xdc : {file_type : xdc}
  98       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  99       - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
 100
 101   arty_a7:
 102     files:
 103       - fpga/arty_a7.xdc : {file_type : xdc}
 104       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 105       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 106
 107   cmod_a7-35:
 108     files:
 109       - fpga/cmod_a7-35.xdc : {file_type : xdc}
 110       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
 111       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
 112
 113   litedram:
 114       depend : [":microwatt:litedram"]
 115
 116   liteeth:
 117       depend : [":microwatt:liteeth"]
 118
 119   uart16550:
 120       depend : ["::uart16550"]
 121
 122 targets:
 123   nexys_a7:
 124     default_tool: vivado
 125     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 126     parameters :
 127       - memory_size
 128       - ram_init_file
 129       - clk_input
 130       - clk_frequency
 131       - disable_flatten_core
 132       - log_length=2048
 133       - uart_is_16550
 134       - has_fpu
 135       - has_btc
 136     tools:
 137       vivado: {part : xc7a100tcsg324-1}
 138     toplevel : toplevel
 139
 140   acorn-cle-215-nodram:
 141     default_tool: vivado
 142     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 143     parameters :
 144       - memory_size
 145       - ram_init_file
 146       - clk_input
 147       - clk_frequency
 148       - disable_flatten_core
 149       - spi_flash_offset=10485760
 150       - log_length=2048
 151       - uart_is_16550
 152     tools:
 153       vivado: {part : xc7a200tsbg484-2}
 154     toplevel : toplevel
 155
 156   genesys2-nodram:
 157     default_tool: vivado
 158     filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 159     parameters :
 160       - memory_size
 161       - ram_init_file
 162       - clk_frequency
 163       - use_litedram=false
 164       - no_bram=false
 165       - disable_flatten_core
 166       - spi_flash_offset=10485760
 167       - log_length=2048
 168       - uart_is_16550=false
 169     tools:
 170       vivado: {part : xc7k325tffg900-2}
 171     toplevel : toplevel
 172
 173   acorn-cle-215:
 174     default_tool: vivado
 175     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 176     parameters :
 177       - memory_size
 178       - ram_init_file
 179       - use_litedram=true
 180       - disable_flatten_core
 181       - no_bram
 182       - spi_flash_offset=10485760
 183       - log_length=2048
 184       - uart_is_16550
 185     generate: [litedram_acorn_cle_215]
 186     tools:
 187       vivado: {part : xc7a200tsbg484-2}
 188     toplevel : toplevel
 189
 190   genesys2:
 191     default_tool: vivado
 192     filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 193     parameters :
 194       - memory_size
 195       - ram_init_file
 196       - use_litedram=true
 197       - disable_flatten_core
 198       - no_bram
 199       - spi_flash_offset=10485760
 200       - log_length=2048
 201       - uart_is_16550=false
 202     generate: [litedram_genesys2]
 203     tools:
 204       vivado: {part : xc7k325tffg900-2}
 205     toplevel : toplevel
 206
 207   nexys_video-nodram:
 208     default_tool: vivado
 209     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 210     parameters :
 211       - memory_size
 212       - ram_init_file
 213       - clk_input
 214       - clk_frequency
 215       - disable_flatten_core
 216       - spi_flash_offset=10485760
 217       - log_length=2048
 218       - uart_is_16550
 219       - has_fpu
 220       - has_btc
 221     tools:
 222       vivado: {part : xc7a200tsbg484-1}
 223     toplevel : toplevel
 224
 225   nexys_video:
 226     default_tool: vivado
 227     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 228     parameters:
 229       - memory_size
 230       - ram_init_file
 231       - use_litedram=true
 232       - disable_flatten_core
 233       - no_bram
 234       - spi_flash_offset=10485760
 235       - log_length=2048
 236       - uart_is_16550
 237       - has_fpu
 238       - has_btc
 239     generate: [litedram_nexys_video]
 240     tools:
 241       vivado: {part : xc7a200tsbg484-1}
 242     toplevel : toplevel
 243
 244   arty_a7-35-nodram:
 245     default_tool: vivado
 246     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 247     parameters :
 248       - memory_size
 249       - ram_init_file
 250       - clk_input
 251       - clk_frequency
 252       - disable_flatten_core
 253       - spi_flash_offset=3145728
 254       - log_length=512
 255       - uart_is_16550
 256       - has_uart1
 257       - has_fpu=false
 258       - has_btc=false
 259     tools:
 260       vivado: {part : xc7a35ticsg324-1L}
 261     toplevel : toplevel
 262
 263   arty_a7-35:
 264     default_tool: vivado
 265     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 266     parameters :
 267       - memory_size
 268       - ram_init_file
 269       - use_litedram=true
 270       - use_liteeth=true
 271       - disable_flatten_core
 272       - no_bram
 273       - spi_flash_offset=3145728
 274       - log_length=512
 275       - uart_is_16550
 276       - has_uart1
 277       - has_fpu=false
 278       - has_btc=false
 279     generate: [litedram_arty, liteeth_arty]
 280     tools:
 281       vivado: {part : xc7a35ticsg324-1L}
 282     toplevel : toplevel
 283
 284   arty_a7-100-nodram:
 285     default_tool: vivado
 286     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 287     parameters :
 288       - memory_size
 289       - ram_init_file
 290       - clk_input
 291       - clk_frequency
 292       - disable_flatten_core
 293       - spi_flash_offset=4194304
 294       - log_length=2048
 295       - uart_is_16550
 296       - has_uart1
 297       - has_fpu
 298       - has_btc
 299     tools:
 300       vivado: {part : xc7a100ticsg324-1L}
 301     toplevel : toplevel
 302
 303   arty_a7-100:
 304     default_tool: vivado
 305     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 306     parameters:
 307       - memory_size
 308       - ram_init_file
 309       - use_litedram=true
 310       - use_liteeth=true
 311       - disable_flatten_core
 312       - no_bram
 313       - spi_flash_offset=4194304
 314       - log_length=2048
 315       - uart_is_16550
 316       - has_uart1
 317       - has_fpu
 318       - has_btc
 319     generate: [litedram_arty, liteeth_arty]
 320     tools:
 321       vivado: {part : xc7a100ticsg324-1L}
 322     toplevel : toplevel
 323
 324   cmod_a7-35:
 325     default_tool: vivado
 326     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 327     parameters :
 328       - memory_size
 329       - ram_init_file
 330       - reset_low=false
 331       - clk_input=12000000
 332       - clk_frequency
 333       - disable_flatten_core
 334       - log_length=512
 335       - uart_is_16550
 336       - has_fpu=false
 337       - has_btc=false
 338     tools:
 339       vivado: {part : xc7a35tcpg236-1}
 340     toplevel : toplevel
 341
 342   synth:
 343     filesets: [core, soc, xilinx_specific]
 344     tools:
 345       vivado: {pnr : none}
 346     toplevel: core
 347
 348 generate:
 349   litedram_arty:
 350     generator: litedram_gen
 351     parameters: {board : arty}
 352
 353   liteeth_arty:
 354     generator: liteeth_gen
 355     parameters: {board : arty}
 356
 357   litedram_nexys_video:
 358     generator: litedram_gen
 359     parameters: {board : nexys-video}
 360
 361   litedram_acorn_cle_215:
 362     generator: litedram_gen
 363     parameters: {board : acorn-cle-215}
 364
 365   litedram_genesys2:
 366     generator: litedram_gen
 367     parameters: {board : genesys2}
 368
 369 parameters:
 370   memory_size:
 371     datatype    : int
 372     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 373     paramtype   : generic
 374     default     : 16384
 375
 376   ram_init_file:
 377     datatype    : file
 378     description : Initial on-chip RAM contents
 379     paramtype   : generic
 380
 381   reset_low:
 382     datatype    : bool
 383     description : External reset button polarity
 384     paramtype   : generic
 385
 386   clk_input:
 387     datatype    : int
 388     description : Clock input frequency in HZ (for top-generic based boards)
 389     paramtype   : generic
 390     default     : 100000000
 391
 392   clk_frequency:
 393     datatype    : int
 394     description : Generated system clock frequency in HZ (for top-generic based boards)
 395     paramtype   : generic
 396     default     : 100000000
 397
 398   has_fpu:
 399     datatype    : bool
 400     description : Include a floating-point unit in the core
 401     paramtype   : generic
 402     default     : true
 403
 404   has_btc:
 405     datatype    : bool
 406     description : Include a branch target cache in the core
 407     paramtype   : generic
 408     default     : true
 409
 410   disable_flatten_core:
 411     datatype    : bool
 412     description : Prevent Vivado from flattening the main core components
 413     paramtype   : generic
 414     default     : false
 415
 416   use_litedram:
 417     datatype    : bool
 418     description : Use liteDRAM
 419     paramtype   : generic
 420     default     : false
 421
 422   use_liteeth:
 423     datatype    : bool
 424     description : Use liteEth
 425     paramtype   : generic
 426     default     : false
 427
 428   uart_is_16550:
 429     datatype    : bool
 430     description : Use 16550-compatible UART from OpenCores
 431     paramtype   : generic
 432     default     : true
 433
 434   has_uart1:
 435     datatype    : bool
 436     description : Enable second UART (always 16550-compatible)
 437     paramtype   : generic
 438     default     : false
 439
 440   no_bram:
 441     datatype    : bool
 442     description : No internal block RAM (only DRAM and init code carrying payload)
 443     paramtype   : generic
 444     default     : false
 445
 446   spi_flash_offset:
 447     datatype    : int
 448     description : Offset (in bytes) in the SPI flash of the code payload to run
 449     paramtype   : generic
 450
 451   log_length:
 452     datatype    : int
 453     description : Length of the core log buffer in entries (32 bytes each)
 454     paramtype   : generic