Add Tercel PHY reset synchronization
[microwatt.git] / fpga /
2022-03-01 Raptor Engineering... [WIP] Add initial version of Aquila LPC slave core
2022-03-01 Raptor Engineering... Add missing mapping between HAS and USE for Liteeth...
2022-02-23 Raptor Engineering... Add Tercel support to Arty
2022-02-23 Raptor Engineering... Add initial Tercel support for Arctic Tern
2022-02-22 Raptor Engineering... Add initial Arctic Tern support
2022-02-22 Raptor Engineering... Extend LiteDRAM VHDL wrapper to allow more than one...
2021-02-08 Michael NeulingMerge pull request #268 from paulusmack/btc
2021-02-08 Michael NeulingMerge pull request #273 from antonblanchard/wishbone...
2021-02-08 Michael NeulingMerge pull request #267 from paulusmack/master
2021-01-18 Paul Mackerrasfetch1: Implement a simple branch target cache
2021-01-15 Paul MackerrasArty A7: Document pin connections for on-board headers
2020-12-08 Anton BlanchardMerge pull request #255 from antonblanchard/log-length
2020-12-08 Anton BlanchardAdd LOG_LENGTH to top-generic.vhdl
2020-09-17 Michael NeulingMerge pull request #245 from paulusmack/fpu
2020-09-03 Paul Mackerrascore: Add support for floating-point loads and stores
2020-08-13 Michael NeulingMerge pull request #235 from paulusmack/master
2020-08-13 Michael NeulingMerge pull request #236 from ozbenh/targets
2020-08-07 Boris Shingarovfpga: Add support for Genesys2
2020-08-07 Benjamin Herrenschmidtacorn: Add support for the Acorn CLE 215+
2020-08-07 Michael NeulingMerge pull request #229 from ozbenh/litedram
2020-08-06 Paul MackerrasAdd random number generator and implement the darn...
2020-07-09 Michael NeulingMerge pull request #228 from ozbenh/misc
2020-07-09 Michael NeulingMerge pull request #222 from iamjpn/master
2020-07-08 Benjamin Herrenschmidtlitedram: l2: Add support for more geometries
2020-07-08 Benjamin Herrenschmidtcorefile/nexys_video: Parameter fixes
2020-07-08 Benjamin Herrenschmidtfpga: nexys-video: Wire up core_alt_reset
2020-07-08 Benjamin Herrenschmidtnexys_video: Fix nexys-video build
2020-07-08 Paul MackerrasMerge pull request #223 from mikey/ecp5
2020-07-07 Michael NeulingAdd PLL for ECP5 device
2020-06-30 Paul MackerrasMerge pull request #206 from Jbalkind/icachecleanup
2020-06-29 Michael NeulingMerge pull request #213 from ozbenh/uart16550
2020-06-29 Michael NeulingMerge pull request #212 from ozbenh/liteeth
2020-06-25 Benjamin Herrenschmidtuart: Make 16550 the default
2020-06-23 Benjamin Herrenschmidtuart: Import and hook up opencore 16550 compatible...
2020-06-23 Benjamin Herrenschmidtliteeth: Hook up LiteX LiteEth ethernet controller
2020-06-23 Michael NeulingMerge pull request #211 from shenki/spi-constraint
2020-06-23 Joel Stanleyspi: Fix dat_i_l constraints
2020-06-19 Michael NeulingMerge pull request #208 from paulusmack/faster
2020-06-17 Paul MackerrasMerge pull request #207 from ozbenh/misc
2020-06-16 Paul MackerrasMake LOG_LENGTH configurable per FPGA variant
2020-06-14 Benjamin Herrenschmidtsoc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
2020-06-13 Benjamin Herrenschmidtsoc: Don't require dram wishbones signals to be wired...
2020-06-13 Benjamin Herrenschmidtsoc: Add defaults for some input signals
2020-06-13 Benjamin Herrenschmidtsoc: Remove unused RESET_LOW generic
2020-06-13 Paul MackerrasMerge pull request #205 from ozbenh/timing
2020-06-13 Paul MackerrasMerge pull request #204 from ozbenh/spi
2020-06-13 Benjamin Herrenschmidtuart: Remove combinational loops on ack and stall signal
2020-06-12 Paul MackerrasMerge pull request #198 from ozbenh/litedram
2020-06-12 Benjamin Herrenschmidtspi: Add SPI Flash controller
2020-06-12 Benjamin Herrenschmidtarty/nexys-video: Update XDC
2020-06-10 Paul MackerrasMerge pull request #194 from ozbenh/misc
2020-06-10 Benjamin Herrenschmidtlitedram: Remove remnants of riscv-inits
2020-06-05 Paul MackerrasMerge pull request #191 from ozbenh/litedram
2020-06-05 Paul MackerrasMerge pull request #183 from shawnanastasio/addpcis
2020-06-05 Benjamin Herrenschmidtlitedram: Add support for booting without BRAM
2020-06-03 Paul MackerrasMerge pull request #168 from shenki/flash-arty
2020-06-02 Anton BlanchardMerge pull request #178 from antonblanchard/intercon
2020-05-25 Benjamin Herrenschmidtsoc: Rework interconnect
2020-05-21 Anton BlanchardMerge pull request #180 from antonblanchard/Makefile...
2020-05-20 Anton BlanchardExit cleanly from testbench on success
2020-05-19 Anton BlanchardMerge pull request #173 from Jbalkind/core-vcs-syntax
2020-05-19 Anton BlanchardMerge pull request #177 from antonblanchard/litedram
2020-05-19 Anton BlanchardMerge branch 'master' into litedram
2020-05-19 Anton BlanchardMerge pull request #176 from antonblanchard/console...
2020-05-19 Anton BlanchardMerge pull request #174 from antonblanchard/yosys-fixes
2020-05-19 Anton BlanchardSome yosys fixes
2020-05-16 Benjamin Herrenschmidtarty/nexys: Rework reset with litedram
2020-05-16 Benjamin Herrenschmidtsoc_reset: Use counters, add synchronizers
2020-05-16 Benjamin Herrenschmidtlitedram: Update to new LiteX/LiteDRAM version
2020-05-15 Benjamin Herrenschmidtpp_soc_uart: Fix rx synchronizers and ensure stable...
2020-05-15 Benjamin Herrenschmidtpp_fifo: Fix full fifo losing all data on simultaneous...
2020-05-14 Paul MackerrasMerge branch 'mmu'
2020-05-14 Anton BlanchardMerge pull request #170 from antonblanchard/litedram
2020-05-08 Benjamin Herrenschmidthello_world: Use new headers and frequency from syscon
2020-05-08 Benjamin Herrenschmidtsyscon: Add syscon registers
2020-05-08 Benjamin Herrenschmidtfpga: Hookup nexys-video to litedram
2020-05-08 Benjamin Herrenschmidtfpga: Hookup Arty to litedram
2020-05-08 Benjamin Herrenschmidtsoc: Add DRAM address decoding
2020-05-08 Benjamin HerrenschmidtUpdate hello_world for 100Mhz clock
2020-01-21 Anton BlanchardMerge pull request #134 from paulusmack/master
2020-01-19 Anton BlanchardMerge pull request #136 from antonblanchard/uart-rx...
2020-01-19 Anton BlanchardAdd a few FFs on the RX input to avoid metastability...
2020-01-19 Anton BlanchardMerge pull request #139 from antonblanchard/reduce-mem
2020-01-19 Anton BlanchardReduce simulated and default FPGA RAM to 384kB
2020-01-11 Anton BlanchardMerge pull request #133 from antonblanchard/ghdl-synth
2020-01-11 Anton BlanchardFix some ghdlsynth issues with fpga_bram
2019-12-09 Anton BlanchardMerge pull request #122 from paulusmack/benh-sprs
2019-12-09 Anton BlanchardMerge pull request #123 from antonblanchard/spi-conf
2019-12-09 Anton BlanchardAdd SPI configuration to Xilinx constraint files
2019-11-15 Anton BlanchardMerge pull request #118 from antonblanchard/bus-pipeline
2019-10-30 Benjamin Herrenschmidtram: Rework main RAM interface
2019-10-30 Benjamin Herrenschmidtram: Add block RAM pipelining
2019-10-30 Benjamin HerrenschmidtAdd option to not flatten hierarchy
2019-10-30 Benjamin Herrenschmidtfpga/bram: Generate stall signal
2019-10-30 Benjamin Herrenschmidtpp_uart: reformat
2019-10-13 Anton BlanchardMerge pull request #96 from antonblanchard/clk_gen_bypa...
2019-10-13 Anton BlanchardFix clk_gen_bypass
2019-10-13 Anton BlanchardMerge pull request #94 from antonblanchard/icbi-nop
2019-10-13 Anton BlanchardMerge pull request #93 from antonblanchard/fifo-fix
2019-10-13 Anton Blanchardfifo: Reformat
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