src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 '''
  43 footer = '''
  44    endmodule
  45 endpackage
  46 '''
  47
  48
  49 def pinmuxgen(pth=None, verify=True):
  50     """ populating the file with the code
  51     """
  52
  53     p = Parse(pth, verify)
  54     iocells = Interfaces()
  55     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  56     ifaces = Interfaces(pth)
  57     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  58     init(p, ifaces)
  59
  60     bp = 'bsv_src'
  61     if pth:
  62         bp = os.path.join(pth, bp)
  63     if not os.path.exists(bp):
  64         os.makedirs(bp)
  65     bl = os.path.join(bp, 'bsv_lib')
  66     if not os.path.exists(bl):
  67         os.makedirs(bl)
  68
  69     cwd = os.path.split(__file__)[0]
  70
  71     # copy over template and library files
  72     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  73                     os.path.join(bp, 'Makefile'))
  74     cwd = os.path.join(cwd, 'bsv_lib')
  75     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
  76                   'gpio.bsv', 'mux.bsv',
  77                   'AXI4_Types.bsv', 'defined_types.bsv',
  78                   'AXI4_Fabric.bsv', 'Uart16550.bsv',
  79                   'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
  80                   'Uart_bs.bsv', 'RS232_modified.bsv',
  81                   'AXI4Lite_AXI4_Bridge.bsv',
  82                   'I2C_top.bsv', 'I2C_Defs.bsv',
  83                   'plic.bsv', 'Cur_Cycle.bsv',
  84                   'ClockDiv.bsv', 'axi_addr_generator.bsv',
  85                   'jtagdtm_new.bsv', 'jtagdefines.bsv',
  86                   'pwm.bsv', 'qspi.bsv', 'qspi.defs',
  87                   ]:
  88         shutil.copyfile(os.path.join(cwd, fname),
  89                         os.path.join(bl, fname))
  90
  91     bus = os.path.join(bp, 'busenable.bsv')
  92     pmp = os.path.join(bp, 'pinmux.bsv')
  93     ptp = os.path.join(bp, 'PinTop.bsv')
  94     bvp = os.path.join(bp, 'bus.bsv')
  95     idef = os.path.join(bp, 'instance_defines.bsv')
  96     slow = os.path.join(bp, 'slow_peripherals.bsv')
  97     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  98
  99     write_pmp(pmp, p, ifaces, iocells)
 100     write_ptp(ptp, p, ifaces)
 101     write_bvp(bvp, p, ifaces)
 102     write_bus(bus, p, ifaces)
 103     write_instances(idef, p, ifaces)
 104     write_slow(slow, slowt, p, ifaces, iocells)
 105
 106
 107 def write_slow(slow, template, p, ifaces, iocells):
 108     """ write out the slow_peripherals.bsv file.
 109         joins all the peripherals together into one AXI Lite interface
 110     """
 111     with open(template) as bsv_file:
 112         template = bsv_file.read()
 113     imports = ifaces.slowimport()
 114     ifdecl = ifaces.slowifdeclmux()
 115     regdef = ifaces.axi_reg_def()
 116     slavedecl = ifaces.axi_slave_idx()
 117     fnaddrmap = ifaces.axi_addr_map()
 118     mkslow = ifaces.mkslow_peripheral()
 119     mkcon = ifaces.mk_connection()
 120     mkcellcon = ifaces.mk_cellconn()
 121     pincon = ifaces.mk_pincon()
 122     with open(slow, "w") as bsv_file:
 123         bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
 124                                        fnaddrmap, mkslow, mkcon, mkcellcon,
 125                                        pincon))
 126
 127
 128 def write_bus(bus, p, ifaces):
 129     # package and interface declaration followed by
 130     # the generic io_cell definition
 131     with open(bus, "w") as bsv_file:
 132         ifaces.busfmt(bsv_file)
 133
 134
 135 def write_pmp(pmp, p, ifaces, iocells):
 136     # package and interface declaration followed by
 137     # the generic io_cell definition
 138     with open(pmp, "w") as bsv_file:
 139         bsv_file.write(header)
 140
 141         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 142         bsv_file.write('''\
 143    interface MuxSelectionLines;
 144
 145       // declare the method which will capture the user pin-mux
 146       // selection values.The width of the input is dependent on the number
 147       // of muxes happening per IO. For now we have a generalized width
 148       // where each IO will have the same number of muxes.''')
 149
 150         for cell in p.muxed_cells:
 151             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 152
 153         bsv_file.write("\n      endinterface\n")
 154
 155         bsv_file.write('''
 156
 157       interface IOCellSide;
 158       // declare the interface to the IO cells.
 159       // Each IO cell will have 1 input field (output from pin mux)
 160       // and an output and out-enable field (input to pinmux)''')
 161
 162         # == create method definitions for all iocell interfaces ==#
 163         iocells.ifacefmt(bsv_file)
 164
 165         # ===== finish interface definition and start module definition=======
 166         bsv_file.write("\n      endinterface\n")
 167
 168         # ===== io cell definition =======
 169         bsv_file.write('''
 170
 171       interface PeripheralSide;
 172       // declare the interface to the peripherals
 173       // Each peripheral's function will be either an input, output
 174       // or be bi-directional.  an input field will be an output from the
 175       // peripheral and an output field will be an input to the peripheral.
 176       // Bi-directional functions also have an output-enable (which
 177       // again comes *in* from the peripheral)''')
 178         # ==============================================================
 179
 180         # == create method definitions for all peripheral interfaces ==#
 181         ifaces.ifacefmt(bsv_file)
 182         bsv_file.write("\n      endinterface\n")
 183
 184         # ===== finish interface definition and start module definition=======
 185         bsv_file.write('''
 186
 187    interface Ifc_pinmux;
 188       // this interface controls how each IO cell is routed.  setting
 189       // any given IO cell's mux control value will result in redirection
 190       // of not just the input or output to different peripheral functions
 191       // but also the *direction* control - if appropriate - as well.
 192       interface MuxSelectionLines mux_lines;
 193
 194       // this interface contains the inputs, outputs and direction-control
 195       // lines for all peripherals.  GPIO is considered to also be just
 196       // a peripheral because it also has in, out and direction-control.
 197       interface PeripheralSide peripheral_side;
 198
 199       // this interface is to be linked to the individual IO cells.
 200       // if looking at a "non-muxed" GPIO design, basically the
 201       // IO cell input, output and direction-control wires are cut
 202       // (giving six pairs of dangling wires, named left and right)
 203       // these iocells are routed in their place on one side ("left")
 204       // and the matching *GPIO* peripheral interfaces in/out/dir
 205       // connect to the OTHER side ("right").  the result is that
 206       // the muxer settings end up controlling the routing of where
 207       // the I/O from the IOcell actually goes.
 208       interface IOCellSide iocell_side;
 209    endinterface
 210    (*synthesize*)
 211    module mkpinmux(Ifc_pinmux);
 212 ''')
 213         # ====================================================================
 214
 215         # ======================= create wire and registers =================#
 216         bsv_file.write('''
 217       // the followins wires capture the pin-mux selection
 218       // values for each mux assigned to a CELL
 219 ''')
 220         for cell in p.muxed_cells:
 221             bsv_file.write(mux_interface.wirefmt(
 222                 cell[0], cell_bit_width))
 223
 224         iocells.wirefmt(bsv_file)
 225         ifaces.wirefmt(bsv_file)
 226
 227         bsv_file.write("\n")
 228         # ====================================================================
 229         # ========================= Actual pinmuxing ========================#
 230         bsv_file.write('''
 231       /*====== This where the muxing starts for each io-cell======*/
 232       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 233 ''')
 234         bsv_file.write(p.pinmux)
 235         bsv_file.write('''
 236       /*============================================================*/
 237 ''')
 238         # ====================================================================
 239         # ================= interface definitions for each method =============#
 240         bsv_file.write('''
 241     interface mux_lines = interface MuxSelectionLines
 242 ''')
 243         for cell in p.muxed_cells:
 244             bsv_file.write(
 245                 mux_interface.ifacedef(
 246                     cell[0], cell_bit_width))
 247         bsv_file.write("\n    endinterface;")
 248
 249         bsv_file.write('''
 250     interface iocell_side = interface IOCellSide
 251 ''')
 252         iocells.ifacedef(bsv_file)
 253         bsv_file.write("\n     endinterface;")
 254
 255         bsv_file.write('''
 256     interface peripheral_side = interface PeripheralSide
 257 ''')
 258         ifaces.ifacedef(bsv_file)
 259         bsv_file.write("\n     endinterface;")
 260
 261         bsv_file.write(footer)
 262         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 263         # ======================================================================
 264
 265
 266 def write_ptp(ptp, p, ifaces):
 267     with open(ptp, 'w') as bsv_file:
 268         bsv_file.write(copyright + '''
 269 package PinTop;
 270     import pinmux::*;
 271     interface Ifc_PintTop;
 272         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 273         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 274         interface PeripheralSide peripheral_side;
 275     endinterface
 276
 277     module mkPinTop(Ifc_PintTop);
 278         // instantiate the pin-mux module here
 279         Ifc_pinmux pinmux <-mkpinmux;
 280
 281         // declare the registers which will be used to mux the IOs
 282 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 283
 284         cell_bit_width = str(p.cell_bitwidth)
 285         for cell in p.muxed_cells:
 286             bsv_file.write('''
 287                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 288                 cell_bit_width, cell[0]))
 289
 290         bsv_file.write('''
 291         // rule to connect the registers to the selection lines of the
 292         // pin-mux module
 293         rule connect_selection_registers;''')
 294
 295         for cell in p.muxed_cells:
 296             bsv_file.write('''
 297           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 298
 299         bsv_file.write('''
 300         endrule
 301         // method definitions for the write user interface
 302         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 303           Bool err=False;
 304           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 305                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 306         index = 0
 307         for cell in p.muxed_cells:
 308             bsv_file.write('''
 309             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 310             index = index + 1
 311
 312         bsv_file.write('''
 313             default: err=True;
 314           endcase
 315           return err;
 316         endmethod''')
 317
 318         bsv_file.write('''
 319         // method definitions for the read user interface
 320         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 321           Bool err=False;
 322           Bit#(32) data=0;
 323           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 324                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 325         index = 0
 326         for cell in p.muxed_cells:
 327             bsv_file.write('''
 328                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 329             index = index + 1
 330
 331         bsv_file.write('''
 332             default:err=True;
 333           endcase
 334           return tuple2(err,data);
 335         endmethod
 336         interface peripheral_side=pinmux.peripheral_side;
 337     endmodule
 338 endpackage
 339 ''')
 340
 341
 342 def write_bvp(bvp, p, ifaces):
 343     # ######## Generate bus transactors ################
 344     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 345               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 346     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 347         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 348
 349     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 350     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 351     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 352               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 353     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 354         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 355     with open(bvp, 'w') as bsv_file:
 356         # assume here that all muxes have a 1:1 gpio
 357         cfg = []
 358         decl = []
 359         idec = []
 360         iks = sorted(ifaces.keys())
 361         for iname in iks:
 362             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 363                 continue
 364             bank = iname[4:]
 365             ifc = ifaces[iname]
 366             npins = len(ifc.pinspecs)
 367             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 368                                       0,  # USERSPACE
 369                                       bank, npins))
 370             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 371                                      0,  # USERSPACE
 372                                      bank, npins))
 373             decl.append(gpiodec.format(npins, bank))
 374             decl.append(muxdec .format(npins, bank))
 375             idec.append(gpioifc.format(bank))
 376             idec.append(muxifc.format(bank))
 377         print dir(ifaces)
 378         print ifaces.items()
 379         print dir(ifaces['gpioa'])
 380         print ifaces['gpioa'].pinspecs
 381         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 382         gpiocfg = '\n'.join(cfg)
 383         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 384     # ##################################################
 385
 386
 387 def write_instances(idef, p, ifaces):
 388     with open(idef, 'w') as bsv_file:
 389         txt = '''\
 390 `define ADDR {0}
 391 `define PADDR {0}
 392 `define DATA {1}
 393 `define Reg_width {1}
 394 `define USERSPACE 0
 395
 396 // TODO: work out if these are needed
 397 `define PWM_AXI4Lite
 398 `define PRFDEPTH 6
 399 `define VADDR 39
 400 `define DCACHE_BLOCK_SIZE 4
 401 `define DCACHE_WORD_SIZE 8
 402 `define PERFMONITORS                            64
 403 `define DCACHE_WAYS 4
 404 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 405 `define PLIC
 406         `define PLICBase                'h0c000000
 407         `define PLICEnd         'h10000000
 408 `define INTERRUPT_PINS 64
 409
 410 `define BAUD_RATE 130
 411 `ifdef simulate
 412   `define BAUD_RATE 5 //130 //
 413 `endif
 414 '''
 415         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))