src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 '''
  43 footer = '''
  44    endmodule
  45 endpackage
  46 '''
  47
  48
  49 def pinmuxgen(pth=None, verify=True):
  50     """ populating the file with the code
  51     """
  52
  53     p = Parse(pth, verify)
  54     iocells = Interfaces()
  55     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  56     ifaces = Interfaces(pth)
  57     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  58     init(p, ifaces)
  59
  60     bp = 'bsv_src'
  61     if pth:
  62         bp = os.path.join(pth, bp)
  63     if not os.path.exists(bp):
  64         os.makedirs(bp)
  65     bl = os.path.join(bp, 'bsv_lib')
  66     if not os.path.exists(bl):
  67         os.makedirs(bl)
  68
  69     cwd = os.path.split(__file__)[0]
  70
  71     # copy over template and library files
  72     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  73                     os.path.join(bp, 'Makefile'))
  74     cwd = os.path.join(cwd, 'bsv_lib')
  75     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
  76                   'gpio.bsv',  'mux.bsv']:
  77         shutil.copyfile(os.path.join(cwd, fname),
  78                         os.path.join(bl, fname))
  79
  80     bus = os.path.join(bp, 'busenable.bsv')
  81     pmp = os.path.join(bp, 'pinmux.bsv')
  82     ptp = os.path.join(bp, 'PinTop.bsv')
  83     bvp = os.path.join(bp, 'bus.bsv')
  84
  85     write_pmp(pmp, p, ifaces, iocells)
  86     write_ptp(ptp, p, ifaces)
  87     write_bvp(bvp, p, ifaces)
  88     write_bus(bus, p, ifaces)
  89
  90
  91 def write_bus(bus, p, ifaces):
  92     # package and interface declaration followed by
  93     # the generic io_cell definition
  94     with open(bus, "w") as bsv_file:
  95         ifaces.busfmt(bsv_file)
  96
  97
  98 def write_pmp(pmp, p, ifaces, iocells):
  99     # package and interface declaration followed by
 100     # the generic io_cell definition
 101     with open(pmp, "w") as bsv_file:
 102         bsv_file.write(header)
 103
 104         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 105         bsv_file.write('''\
 106    interface MuxSelectionLines;
 107
 108       // declare the method which will capture the user pin-mux
 109       // selection values.The width of the input is dependent on the number
 110       // of muxes happening per IO. For now we have a generalized width
 111       // where each IO will have the same number of muxes.''')
 112
 113         for cell in p.muxed_cells:
 114             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 115
 116         bsv_file.write("\n      endinterface\n")
 117
 118         bsv_file.write('''
 119
 120       interface IOCellSide;
 121       // declare the interface to the IO cells.
 122       // Each IO cell will have 1 input field (output from pin mux)
 123       // and an output and out-enable field (input to pinmux)''')
 124
 125         # == create method definitions for all iocell interfaces ==#
 126         iocells.ifacefmt(bsv_file)
 127
 128         # ===== finish interface definition and start module definition=======
 129         bsv_file.write("\n      endinterface\n")
 130
 131         # ===== io cell definition =======
 132         bsv_file.write('''
 133
 134       interface PeripheralSide;
 135       // declare the interface to the peripherals
 136       // Each peripheral's function will be either an input, output
 137       // or be bi-directional.  an input field will be an output from the
 138       // peripheral and an output field will be an input to the peripheral.
 139       // Bi-directional functions also have an output-enable (which
 140       // again comes *in* from the peripheral)''')
 141         # ==============================================================
 142
 143         # == create method definitions for all peripheral interfaces ==#
 144         ifaces.ifacefmt(bsv_file)
 145         bsv_file.write("\n      endinterface\n")
 146
 147         # ===== finish interface definition and start module definition=======
 148         bsv_file.write('''
 149
 150    interface Ifc_pinmux;
 151       // this interface controls how each IO cell is routed.  setting
 152       // any given IO cell's mux control value will result in redirection
 153       // of not just the input or output to different peripheral functions
 154       // but also the *direction* control - if appropriate - as well.
 155       interface MuxSelectionLines mux_lines;
 156
 157       // this interface contains the inputs, outputs and direction-control
 158       // lines for all peripherals.  GPIO is considered to also be just
 159       // a peripheral because it also has in, out and direction-control.
 160       interface PeripheralSide peripheral_side;
 161
 162       // this interface is to be linked to the individual IO cells.
 163       // if looking at a "non-muxed" GPIO design, basically the
 164       // IO cell input, output and direction-control wires are cut
 165       // (giving six pairs of dangling wires, named left and right)
 166       // these iocells are routed in their place on one side ("left")
 167       // and the matching *GPIO* peripheral interfaces in/out/dir
 168       // connect to the OTHER side ("right").  the result is that
 169       // the muxer settings end up controlling the routing of where
 170       // the I/O from the IOcell actually goes.
 171       interface IOCellSide iocell_side;
 172    endinterface
 173    (*synthesize*)
 174    module mkpinmux(Ifc_pinmux);
 175 ''')
 176         # ====================================================================
 177
 178         # ======================= create wire and registers =================#
 179         bsv_file.write('''
 180       // the followins wires capture the pin-mux selection
 181       // values for each mux assigned to a CELL
 182 ''')
 183         for cell in p.muxed_cells:
 184             bsv_file.write(mux_interface.wirefmt(
 185                 cell[0], cell_bit_width))
 186
 187         iocells.wirefmt(bsv_file)
 188         ifaces.wirefmt(bsv_file)
 189
 190         bsv_file.write("\n")
 191         # ====================================================================
 192         # ========================= Actual pinmuxing ========================#
 193         bsv_file.write('''
 194       /*====== This where the muxing starts for each io-cell======*/
 195       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 196 ''')
 197         bsv_file.write(p.pinmux)
 198         bsv_file.write('''
 199       /*============================================================*/
 200 ''')
 201         # ====================================================================
 202         # ================= interface definitions for each method =============#
 203         bsv_file.write('''
 204     interface mux_lines = interface MuxSelectionLines
 205 ''')
 206         for cell in p.muxed_cells:
 207             bsv_file.write(
 208                 mux_interface.ifacedef(
 209                     cell[0], cell_bit_width))
 210         bsv_file.write("\n    endinterface;")
 211
 212         bsv_file.write('''
 213     interface iocell_side = interface IOCellSide
 214 ''')
 215         iocells.ifacedef(bsv_file)
 216         bsv_file.write("\n     endinterface;")
 217
 218         bsv_file.write('''
 219     interface peripheral_side = interface PeripheralSide
 220 ''')
 221         ifaces.ifacedef(bsv_file)
 222         bsv_file.write("\n     endinterface;")
 223
 224         bsv_file.write(footer)
 225         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 226         # ======================================================================
 227
 228
 229 def write_ptp(ptp, p, ifaces):
 230     with open(ptp, 'w') as bsv_file:
 231         bsv_file.write(copyright + '''
 232 package PinTop;
 233     import pinmux::*;
 234     interface Ifc_PintTop;
 235         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 236         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 237         interface PeripheralSide peripheral_side;
 238     endinterface
 239
 240     module mkPinTop(Ifc_PintTop);
 241         // instantiate the pin-mux module here
 242         Ifc_pinmux pinmux <-mkpinmux;
 243
 244         // declare the registers which will be used to mux the IOs
 245 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 246
 247         cell_bit_width = str(p.cell_bitwidth)
 248         for cell in p.muxed_cells:
 249             bsv_file.write('''
 250                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 251                 cell_bit_width, cell[0]))
 252
 253         bsv_file.write('''
 254         // rule to connect the registers to the selection lines of the
 255         // pin-mux module
 256         rule connect_selection_registers;''')
 257
 258         for cell in p.muxed_cells:
 259             bsv_file.write('''
 260           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 261
 262         bsv_file.write('''
 263         endrule
 264         // method definitions for the write user interface
 265         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 266           Bool err=False;
 267           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 268                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 269         index = 0
 270         for cell in p.muxed_cells:
 271             bsv_file.write('''
 272             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 273             index = index + 1
 274
 275         bsv_file.write('''
 276             default: err=True;
 277           endcase
 278           return err;
 279         endmethod''')
 280
 281         bsv_file.write('''
 282         // method definitions for the read user interface
 283         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 284           Bool err=False;
 285           Bit#(32) data=0;
 286           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 287                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 288         index = 0
 289         for cell in p.muxed_cells:
 290             bsv_file.write('''
 291                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 292             index = index + 1
 293
 294         bsv_file.write('''
 295             default:err=True;
 296           endcase
 297           return tuple2(err,data);
 298         endmethod
 299         interface peripheral_side=pinmux.peripheral_side;
 300     endmodule
 301 endpackage
 302 ''')
 303
 304
 305 def write_bvp(bvp, p, ifaces):
 306     # ######## Generate bus transactors ################
 307     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 308               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 309     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 310         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 311
 312     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 313     muxdec = '\tMUX#({0}) mymux{1} <- mkgpio();'
 314     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 315               '\tinterface bank{0}A_slave=mygpio{0}.axi_slave;'
 316     muxifc = '\tinterface muxb{0}_config=mymux{0}.pad_config;\n' \
 317         '\tinterface muxb{0}A_slave=mymux{0}.axi_slave;'
 318     with open(bvp, 'w') as bsv_file:
 319         # assume here that all muxes have a 1:1 gpio
 320         cfg = []
 321         decl = []
 322         idec = []
 323         iks = sorted(ifaces.keys())
 324         for iname in iks:
 325             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 326                 continue
 327             bank = iname[4:]
 328             ifc = ifaces[iname]
 329             npins = len(ifc.pinspecs)
 330             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 331                                       0,  # USERSPACE
 332                                       bank, npins))
 333             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 334                                      0,  # USERSPACE
 335                                      bank, npins))
 336             decl.append(gpiodec.format(npins, bank))
 337             decl.append(muxdec .format(npins, bank))
 338             idec.append(gpioifc.format(bank))
 339             idec.append(muxifc.format(bank))
 340         print dir(ifaces)
 341         print ifaces.items()
 342         print dir(ifaces['gpioa'])
 343         print ifaces['gpioa'].pinspecs
 344         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 345         gpiocfg = '\n'.join(cfg)
 346         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 347     # ##################################################