src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     shutil.copyfile(os.path.join(cwd, 'Makefile.peripherals.template'),
  78                     os.path.join(bp, 'Makefile.peripherals'))
  79     cwd = os.path.join(cwd, 'bsv_lib')
  80     for fname in []:
  81         shutil.copyfile(os.path.join(cwd, fname),
  82                         os.path.join(bl, fname))
  83
  84     bus = os.path.join(bp, 'busenable.bsv')
  85     pmp = os.path.join(bp, 'pinmux.bsv')
  86     bvp = os.path.join(bp, 'bus.bsv')
  87     idef = os.path.join(bp, 'instance_defines.bsv')
  88     slow = os.path.join(bp, 'slow_peripherals.bsv')
  89     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  90
  91     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  92     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  93
  94     slowid = os.path.join(bp, 'slow_instance_defines.bsv')
  95     slowit = os.path.join(cwd, 'slow_instance_defines_template.bsv')
  96
  97     fastmf = os.path.join(bp, 'fast_memory_map.bsv')
  98     fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
  99
 100     soc = os.path.join(bp, 'socgen.bsv')
 101     soct = os.path.join(cwd, 'soc_template.bsv')
 102
 103     write_pmp(pmp, p, ifaces, iocells)
 104     write_bvp(bvp, p, ifaces)
 105     write_bus(bus, p, ifaces)
 106     write_instances(idef, p, ifaces)
 107     write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells)
 108     write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells)
 109
 110
 111 def write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells):
 112     """ write out the slow_peripherals.bsv file.
 113         joins all the peripherals together into one AXI Lite interface
 114     """
 115     imports = ifaces.slowimport()
 116     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 117     regdef = ifaces.axi_reg_def()
 118     slavedecl = ifaces.axi_slave_idx()
 119     fnaddrmap = ifaces.axi_addr_map()
 120     mkslow = ifaces.mkslow_peripheral()
 121     mkcon = ifaces.mk_connection()
 122     mkcellcon = ifaces.mk_cellconn()
 123     pincon = ifaces.mk_pincon()
 124     inst = ifaces.extifinstance()
 125     inst2 = ifaces.extifinstance2()
 126     mkplic = ifaces.mk_plic()
 127     numsloirqs = ifaces.mk_sloirqsdef()
 128     ifacedef = ifaces.mk_ext_ifacedef()
 129     ifacedef = ifaces.mk_ext_ifacedef()
 130     clockcon = ifaces.mk_slowclk_con()
 131
 132     with open(slow, "w") as bsv_file:
 133         with open(slowt) as f:
 134             slowt = f.read()
 135         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 136                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 137                                     pincon, inst, mkplic,
 138                                     numsloirqs, ifacedef,
 139                                     inst2, clockcon))
 140
 141     with open(slowid, "w") as bsv_file:
 142         with open(slowit) as f:
 143             slowit = f.read()
 144         bsv_file.write(slowit.format(regdef))
 145
 146     with open(slowmf, "w") as bsv_file:
 147         with open(slowmt) as f:
 148             slowmt = f.read()
 149         bsv_file.write(slowmt.format(fnaddrmap, slavedecl))
 150
 151
 152 def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells):
 153     """ write out the soc.bsv file.
 154         joins all the peripherals together as AXI Masters
 155     """
 156     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 157
 158     imports = ifaces.slowimport()
 159     ifdecl = ifaces.fastifdecl()
 160     regdef = ifaces.axi_fastmem_def()
 161     slavedecl = ifaces.axi_fastslave_idx()
 162     mastdecl = ifaces.axi_master_idx()
 163     fnaddrmap = ifaces.axi_fastaddr_map()
 164     mkfast = ifaces.mkfast_peripheral()
 165     mkcon = ifaces.mk_fast_connection()
 166     mkmstcon = ifaces.mk_master_connection()
 167     mkcellcon = ifaces.mk_cellconn()
 168     pincon = ifaces.mk_fast_pincon()
 169     inst = ifaces.extfastifinstance()
 170     mkplic = ifaces.mk_plic()
 171     numsloirqs = ifaces.mk_sloirqsdef()
 172     ifacedef = ifaces.mk_ext_ifacedef()
 173     dma = ifaces.mk_dma_irq()
 174     num_dmachannels = ifaces.num_dmachannels()
 175     clockcon = ifaces.mk_fastclk_con()
 176
 177     with open(soc, "w") as bsv_file:
 178         with open(soct) as f:
 179             soct = f.read()
 180         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 181                                    slavedecl, mastdecl, mkcon,
 182                                    inst, dma, num_dmachannels,
 183                                    pincon, regdef, fnaddrmap,
 184                                    clockcon, mkmstcon,
 185                                    ))
 186
 187     with open(fastmf, "w") as bsv_file:
 188         with open(fastmt) as f:
 189             fastmt = f.read()
 190         bsv_file.write(fastmt.format(regdef, slavedecl, mastdecl, fnaddrmap))
 191
 192
 193 def write_bus(bus, p, ifaces):
 194     # package and interface declaration followed by
 195     # the generic io_cell definition
 196     with open(bus, "w") as bsv_file:
 197         ifaces.busfmt(bsv_file)
 198
 199
 200 def write_pmp(pmp, p, ifaces, iocells):
 201     # package and interface declaration followed by
 202     # the generic io_cell definition
 203     with open(pmp, "w") as bsv_file:
 204         bsv_file.write(header)
 205
 206         bwid_template = 'Bit#(%d)'
 207         bsv_file.write('''\
 208       (*always_ready,always_enabled*)
 209       interface MuxSelectionLines;
 210
 211       // declare the method which will capture the user pin-mux
 212       // selection values.The width of the input is dependent on the number
 213       // of muxes happening per IO. For now we have a generalized width
 214       // where each IO will have the same number of muxes.''')
 215
 216         for cell in p.muxed_cells:
 217             cellnum = cell[0]
 218             bitwidth = p.get_muxbitwidth(cellnum)
 219             if bitwidth == 0:
 220                 continue
 221             cell_bit_width = bwid_template % bitwidth
 222             bsv_file.write(mux_interface.ifacefmt(cellnum, cell_bit_width))
 223
 224         bsv_file.write("\n      endinterface\n")
 225
 226         bsv_file.write('''
 227
 228       interface IOCellSide;
 229       // declare the interface to the IO cells.
 230       // Each IO cell will have 1 input field (output from pin mux)
 231       // and an output and out-enable field (input to pinmux)''')
 232
 233         # == create method definitions for all iocell interfaces ==#
 234         iocells.ifacefmt(bsv_file)
 235
 236         # ===== finish interface definition and start module definition=======
 237         bsv_file.write("\n      endinterface\n")
 238
 239         ifaces.ifacepfmt(bsv_file)
 240         # ===== io cell definition =======
 241         bsv_file.write('''
 242       (*always_ready,always_enabled*)
 243       interface PeripheralSide;
 244       // declare the interface to the peripherals
 245       // Each peripheral's function will be either an input, output
 246       // or be bi-directional.  an input field will be an output from the
 247       // peripheral and an output field will be an input to the peripheral.
 248       // Bi-directional functions also have an output-enable (which
 249       // again comes *in* from the peripheral)''')
 250         # ==============================================================
 251
 252         # == create method definitions for all peripheral interfaces ==#
 253         ifaces.ifacefmt2(bsv_file)
 254         bsv_file.write("\n      endinterface\n")
 255
 256         # ===== finish interface definition and start module definition=======
 257         bsv_file.write('''
 258
 259    interface Ifc_pinmux;
 260       // this interface controls how each IO cell is routed.  setting
 261       // any given IO cell's mux control value will result in redirection
 262       // of not just the input or output to different peripheral functions
 263       // but also the *direction* control - if appropriate - as well.
 264       interface MuxSelectionLines mux_lines;
 265
 266       // this interface contains the inputs, outputs and direction-control
 267       // lines for all peripherals.  GPIO is considered to also be just
 268       // a peripheral because it also has in, out and direction-control.
 269       interface PeripheralSide peripheral_side;
 270
 271       // this interface is to be linked to the individual IO cells.
 272       // if looking at a "non-muxed" GPIO design, basically the
 273       // IO cell input, output and direction-control wires are cut
 274       // (giving six pairs of dangling wires, named left and right)
 275       // these iocells are routed in their place on one side ("left")
 276       // and the matching *GPIO* peripheral interfaces in/out/dir
 277       // connect to the OTHER side ("right").  the result is that
 278       // the muxer settings end up controlling the routing of where
 279       // the I/O from the IOcell actually goes.
 280       interface IOCellSide iocell_side;
 281    endinterface
 282
 283    (*synthesize*)
 284    module mkpinmux(Ifc_pinmux);
 285 ''')
 286         # ====================================================================
 287
 288         # ======================= create wire and registers =================#
 289         bsv_file.write('''
 290       // the followins wires capture the pin-mux selection
 291       // values for each mux assigned to a CELL
 292 ''')
 293         for cell in p.muxed_cells:
 294             cellnum = cell[0]
 295             bitwidth = p.get_muxbitwidth(cellnum)
 296             if bitwidth == 0:
 297                 continue
 298             cell_bit_width = bwid_template % bitwidth
 299             bsv_file.write(mux_interface.wirefmt(cellnum, cell_bit_width))
 300
 301         iocells.wirefmt(bsv_file)
 302         ifaces.wirefmt(bsv_file)
 303
 304         bsv_file.write("\n")
 305         # ====================================================================
 306         # ========================= Actual pinmuxing ========================#
 307         bsv_file.write('''
 308       /*====== This where the muxing starts for each io-cell======*/
 309       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 310       Wire#(Bit#(1)) val1<-mkDWire(1); // need a one
 311 ''')
 312         bsv_file.write(p.pinmux)
 313         bsv_file.write('''
 314       /*============================================================*/
 315 ''')
 316         # ====================================================================
 317         # ================= interface definitions for each method =============#
 318         bsv_file.write('''
 319     interface mux_lines = interface MuxSelectionLines
 320 ''')
 321         for cell in p.muxed_cells:
 322             cellnum = cell[0]
 323             bitwidth = p.get_muxbitwidth(cellnum)
 324             if bitwidth == 0:
 325                 continue
 326             cell_bit_width = bwid_template % bitwidth
 327             bsv_file.write(
 328                 mux_interface.ifacedef(
 329                     cellnum, cell_bit_width))
 330         bsv_file.write("\n    endinterface;")
 331
 332         bsv_file.write('''
 333
 334     interface iocell_side = interface IOCellSide
 335 ''')
 336         iocells.ifacedef(bsv_file)
 337         bsv_file.write("\n     endinterface;")
 338
 339         bsv_file.write('''
 340
 341      interface peripheral_side = interface PeripheralSide
 342 ''')
 343         ifaces.ifacedef2(bsv_file)
 344         bsv_file.write("\n      endinterface;")
 345
 346         bsv_file.write(footer)
 347         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 348         # ======================================================================
 349
 350
 351 def write_bvp(bvp, p, ifaces):
 352     # ######## Generate bus transactors ################
 353     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 354               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 355     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 356         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 357
 358     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 359     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 360     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 361               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 362     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 363         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 364     with open(bvp, 'w') as bsv_file:
 365         # assume here that all muxes have a 1:1 gpio
 366         cfg = []
 367         decl = []
 368         idec = []
 369         iks = sorted(ifaces.keys())
 370         for iname in iks:
 371             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 372                 continue
 373             bank = iname[4:]
 374             ifc = ifaces[iname]
 375             npins = len(ifc.pinspecs)
 376             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 377                                       0,  # USERSPACE
 378                                       bank, npins))
 379             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 380                                      0,  # USERSPACE
 381                                      bank, npins))
 382             decl.append(gpiodec.format(npins, bank))
 383             decl.append(muxdec .format(npins, bank))
 384             idec.append(gpioifc.format(bank))
 385             idec.append(muxifc.format(bank))
 386         print dir(ifaces)
 387         print ifaces.items()
 388         print dir(ifaces['gpioa'])
 389         print ifaces['gpioa'].pinspecs
 390         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 391         gpiocfg = '\n'.join(cfg)
 392         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 393     # ##################################################
 394
 395
 396 def write_instances(idef, p, ifaces):
 397     with open(idef, 'w') as bsv_file:
 398         txt = '''\
 399 `define ADDR {0}
 400 `define PADDR {2}
 401 `define DATA {1}
 402 `define Reg_width {1}
 403 `define USERSPACE 0
 404 `define RV64
 405
 406 // TODO: work out if these are needed
 407 `define PWM_AXI4Lite
 408 `define PRFDEPTH 6
 409 `define VADDR 39
 410 `define DCACHE_BLOCK_SIZE 4
 411 `define DCACHE_WORD_SIZE 8
 412 `define PERFMONITORS                            64
 413 `define DCACHE_WAYS 4
 414 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 415
 416 // CLINT
 417     `define ClintBase       'h02000000
 418     `define ClintEnd        'h020BFFFF
 419
 420 `define PLIC
 421         `define PLICBase                'h0c000000
 422         `define PLICEnd         'h10000000
 423 `define INTERRUPT_PINS 64
 424
 425 `define BAUD_RATE 130
 426 `ifdef simulate
 427   `define BAUD_RATE 5 //130 //
 428 `endif
 429 '''
 430         bsv_file.write(txt.format(p.ADDR_WIDTH,
 431                                   p.DATA_WIDTH,
 432                                   p.PADDR_WIDTH))