src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     soc = os.path.join(bp, 'soc.bsv')
  90     soct = os.path.join(cwd, 'soc_template.bsv')
  91
  92     write_pmp(pmp, p, ifaces, iocells)
  93     write_ptp(ptp, p, ifaces)
  94     write_bvp(bvp, p, ifaces)
  95     write_bus(bus, p, ifaces)
  96     write_instances(idef, p, ifaces)
  97     write_slow(slow, slowt, p, ifaces, iocells)
  98     write_soc(soc, soct, p, ifaces, iocells)
  99
 100
 101 def write_slow(slow, slowt, p, ifaces, iocells):
 102     """ write out the slow_peripherals.bsv file.
 103         joins all the peripherals together into one AXI Lite interface
 104     """
 105     with open(slowt) as bsv_file:
 106         slowt = bsv_file.read()
 107     imports = ifaces.slowimport()
 108     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 109     regdef = ifaces.axi_reg_def()
 110     slavedecl = ifaces.axi_slave_idx()
 111     fnaddrmap = ifaces.axi_addr_map()
 112     mkslow = ifaces.mkslow_peripheral()
 113     mkcon = ifaces.mk_connection()
 114     mkcellcon = ifaces.mk_cellconn()
 115     pincon = ifaces.mk_pincon()
 116     inst = ifaces.extifinstance()
 117     mkplic = ifaces.mk_plic()
 118     numsloirqs = ifaces.mk_sloirqsdef()
 119     ifacedef = ifaces.mk_ext_ifacedef()
 120     ifacedef = ifaces.mk_ext_ifacedef()
 121     with open(slow, "w") as bsv_file:
 122         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 123                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 124                                     pincon, inst, mkplic,
 125                                     numsloirqs, ifacedef))
 126
 127 def write_soc(soc, soct, p, ifaces, iocells):
 128     """ write out the soc.bsv file.
 129         joins all the peripherals together as AXI Masters
 130     """
 131     with open(soct) as bsv_file:
 132         soct = bsv_file.read()
 133     imports = ifaces.slowimport()
 134     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 135     regdef = ifaces.axi_reg_def()
 136     slavedecl = ifaces.axi_slave_idx()
 137     fnaddrmap = ifaces.axi_addr_map()
 138     mkslow = ifaces.mkslow_peripheral()
 139     mkcon = ifaces.mk_connection()
 140     mkcellcon = ifaces.mk_cellconn()
 141     pincon = ifaces.mk_pincon()
 142     inst = ifaces.extifinstance()
 143     mkplic = ifaces.mk_plic()
 144     numsloirqs = ifaces.mk_sloirqsdef()
 145     ifacedef = ifaces.mk_ext_ifacedef()
 146     ifacedef = ifaces.mk_ext_ifacedef()
 147     with open(soc, "w") as bsv_file:
 148         bsv_file.write(soct.format(imports, ))#ifdecl, regdef, slavedecl,
 149                                     #fnaddrmap, mkslow, mkcon, mkcellcon,
 150                                     #pincon, inst, mkplic,
 151                                     #numsloirqs, ifacedef))
 152
 153
 154 def write_bus(bus, p, ifaces):
 155     # package and interface declaration followed by
 156     # the generic io_cell definition
 157     with open(bus, "w") as bsv_file:
 158         ifaces.busfmt(bsv_file)
 159
 160
 161 def write_pmp(pmp, p, ifaces, iocells):
 162     # package and interface declaration followed by
 163     # the generic io_cell definition
 164     with open(pmp, "w") as bsv_file:
 165         bsv_file.write(header)
 166
 167         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 168         bsv_file.write('''\
 169       (*always_ready,always_enabled*)
 170       interface MuxSelectionLines;
 171
 172       // declare the method which will capture the user pin-mux
 173       // selection values.The width of the input is dependent on the number
 174       // of muxes happening per IO. For now we have a generalized width
 175       // where each IO will have the same number of muxes.''')
 176
 177         for cell in p.muxed_cells:
 178             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 179
 180         bsv_file.write("\n      endinterface\n")
 181
 182         bsv_file.write('''
 183
 184       interface IOCellSide;
 185       // declare the interface to the IO cells.
 186       // Each IO cell will have 1 input field (output from pin mux)
 187       // and an output and out-enable field (input to pinmux)''')
 188
 189         # == create method definitions for all iocell interfaces ==#
 190         iocells.ifacefmt(bsv_file)
 191
 192         # ===== finish interface definition and start module definition=======
 193         bsv_file.write("\n      endinterface\n")
 194
 195         ifaces.ifacepfmt(bsv_file)
 196         # ===== io cell definition =======
 197         bsv_file.write('''
 198       (*always_ready,always_enabled*)
 199       interface PeripheralSide;
 200       // declare the interface to the peripherals
 201       // Each peripheral's function will be either an input, output
 202       // or be bi-directional.  an input field will be an output from the
 203       // peripheral and an output field will be an input to the peripheral.
 204       // Bi-directional functions also have an output-enable (which
 205       // again comes *in* from the peripheral)''')
 206         # ==============================================================
 207
 208         # == create method definitions for all peripheral interfaces ==#
 209         ifaces.ifacefmt2(bsv_file)
 210         bsv_file.write("\n      endinterface\n")
 211
 212         # ===== finish interface definition and start module definition=======
 213         bsv_file.write('''
 214
 215    interface Ifc_pinmux;
 216       // this interface controls how each IO cell is routed.  setting
 217       // any given IO cell's mux control value will result in redirection
 218       // of not just the input or output to different peripheral functions
 219       // but also the *direction* control - if appropriate - as well.
 220       interface MuxSelectionLines mux_lines;
 221
 222       // this interface contains the inputs, outputs and direction-control
 223       // lines for all peripherals.  GPIO is considered to also be just
 224       // a peripheral because it also has in, out and direction-control.
 225       interface PeripheralSide peripheral_side;
 226
 227       // this interface is to be linked to the individual IO cells.
 228       // if looking at a "non-muxed" GPIO design, basically the
 229       // IO cell input, output and direction-control wires are cut
 230       // (giving six pairs of dangling wires, named left and right)
 231       // these iocells are routed in their place on one side ("left")
 232       // and the matching *GPIO* peripheral interfaces in/out/dir
 233       // connect to the OTHER side ("right").  the result is that
 234       // the muxer settings end up controlling the routing of where
 235       // the I/O from the IOcell actually goes.
 236       interface IOCellSide iocell_side;
 237    endinterface
 238
 239    (*synthesize*)
 240    module mkpinmux(Ifc_pinmux);
 241 ''')
 242         # ====================================================================
 243
 244         # ======================= create wire and registers =================#
 245         bsv_file.write('''
 246       // the followins wires capture the pin-mux selection
 247       // values for each mux assigned to a CELL
 248 ''')
 249         for cell in p.muxed_cells:
 250             bsv_file.write(mux_interface.wirefmt(
 251                 cell[0], cell_bit_width))
 252
 253         iocells.wirefmt(bsv_file)
 254         ifaces.wirefmt(bsv_file)
 255
 256         bsv_file.write("\n")
 257         # ====================================================================
 258         # ========================= Actual pinmuxing ========================#
 259         bsv_file.write('''
 260       /*====== This where the muxing starts for each io-cell======*/
 261       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 262 ''')
 263         bsv_file.write(p.pinmux)
 264         bsv_file.write('''
 265       /*============================================================*/
 266 ''')
 267         # ====================================================================
 268         # ================= interface definitions for each method =============#
 269         bsv_file.write('''
 270     interface mux_lines = interface MuxSelectionLines
 271 ''')
 272         for cell in p.muxed_cells:
 273             bsv_file.write(
 274                 mux_interface.ifacedef(
 275                     cell[0], cell_bit_width))
 276         bsv_file.write("\n    endinterface;")
 277
 278         bsv_file.write('''
 279
 280     interface iocell_side = interface IOCellSide
 281 ''')
 282         iocells.ifacedef(bsv_file)
 283         bsv_file.write("\n     endinterface;")
 284
 285         bsv_file.write('''
 286
 287      interface peripheral_side = interface PeripheralSide
 288 ''')
 289         ifaces.ifacedef2(bsv_file)
 290         bsv_file.write("\n      endinterface;")
 291
 292         bsv_file.write(footer)
 293         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 294         # ======================================================================
 295
 296
 297 def write_ptp(ptp, p, ifaces):
 298     with open(ptp, 'w') as bsv_file:
 299         bsv_file.write(copyright + '''
 300 package PinTop;
 301     import pinmux::*;
 302     interface Ifc_PintTop;
 303         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 304         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 305         interface PeripheralSide peripheral_side;
 306     endinterface
 307
 308     module mkPinTop(Ifc_PintTop);
 309         // instantiate the pin-mux module here
 310         Ifc_pinmux pinmux <-mkpinmux;
 311
 312         // declare the registers which will be used to mux the IOs
 313 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 314
 315         cell_bit_width = str(p.cell_bitwidth)
 316         for cell in p.muxed_cells:
 317             bsv_file.write('''
 318                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 319                 cell_bit_width, cell[0]))
 320
 321         bsv_file.write('''
 322         // rule to connect the registers to the selection lines of the
 323         // pin-mux module
 324         rule connect_selection_registers;''')
 325
 326         for cell in p.muxed_cells:
 327             bsv_file.write('''
 328           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 329
 330         bsv_file.write('''
 331         endrule
 332         // method definitions for the write user interface
 333         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 334           Bool err=False;
 335           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 336                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 337         index = 0
 338         for cell in p.muxed_cells:
 339             bsv_file.write('''
 340             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 341             index = index + 1
 342
 343         bsv_file.write('''
 344             default: err=True;
 345           endcase
 346           return err;
 347         endmethod''')
 348
 349         bsv_file.write('''
 350         // method definitions for the read user interface
 351         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 352           Bool err=False;
 353           Bit#(32) data=0;
 354           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 355                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 356         index = 0
 357         for cell in p.muxed_cells:
 358             bsv_file.write('''
 359                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 360             index = index + 1
 361
 362         bsv_file.write('''
 363             default:err=True;
 364           endcase
 365           return tuple2(err,data);
 366         endmethod
 367         interface peripheral_side=pinmux.peripheral_side;
 368     endmodule
 369 endpackage
 370 ''')
 371
 372
 373 def write_bvp(bvp, p, ifaces):
 374     # ######## Generate bus transactors ################
 375     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 376               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 377     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 378         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 379
 380     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 381     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 382     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 383               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 384     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 385         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 386     with open(bvp, 'w') as bsv_file:
 387         # assume here that all muxes have a 1:1 gpio
 388         cfg = []
 389         decl = []
 390         idec = []
 391         iks = sorted(ifaces.keys())
 392         for iname in iks:
 393             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 394                 continue
 395             bank = iname[4:]
 396             ifc = ifaces[iname]
 397             npins = len(ifc.pinspecs)
 398             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 399                                       0,  # USERSPACE
 400                                       bank, npins))
 401             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 402                                      0,  # USERSPACE
 403                                      bank, npins))
 404             decl.append(gpiodec.format(npins, bank))
 405             decl.append(muxdec .format(npins, bank))
 406             idec.append(gpioifc.format(bank))
 407             idec.append(muxifc.format(bank))
 408         print dir(ifaces)
 409         print ifaces.items()
 410         print dir(ifaces['gpioa'])
 411         print ifaces['gpioa'].pinspecs
 412         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 413         gpiocfg = '\n'.join(cfg)
 414         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 415     # ##################################################
 416
 417
 418 def write_instances(idef, p, ifaces):
 419     with open(idef, 'w') as bsv_file:
 420         txt = '''\
 421 `define ADDR {0}
 422 `define PADDR {0}
 423 `define DATA {1}
 424 `define Reg_width {1}
 425 `define USERSPACE 0
 426
 427 // TODO: work out if these are needed
 428 `define PWM_AXI4Lite
 429 `define PRFDEPTH 6
 430 `define VADDR 39
 431 `define DCACHE_BLOCK_SIZE 4
 432 `define DCACHE_WORD_SIZE 8
 433 `define PERFMONITORS                            64
 434 `define DCACHE_WAYS 4
 435 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 436 `define PLIC
 437         `define PLICBase                'h0c000000
 438         `define PLICEnd         'h10000000
 439 `define INTERRUPT_PINS 64
 440
 441 `define BAUD_RATE 130
 442 `ifdef simulate
 443   `define BAUD_RATE 5 //130 //
 444 `endif
 445 '''
 446         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))