move cell_bit_width function
[pinmux.git] / src / bsv / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import shutil
20 import os
21 import os.path
22 import time
23
24 # project module imports
25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
26 from parse import Parse
27 from bsv.actual_pinmux import init
28 from bsv.bus_transactors import axi4_lite
29
30 copyright = '''
31 /*
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
34
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time.strftime("%c") + '''
37 */
38 '''
39 header = copyright + '''
40 package pinmux;
41
42 // FunctionType: contains the active wires of a function. That INCLUDES
43 // GPIO (as GPIO is also a "Function"). These are what get muxed.
44 // However, only GPIO "Functions" will end up with Register SRAMs.
45 typedef struct{
46 Bit#(1) outputval; // output from function to pad bit2
47 Bit#(1) inputval; // input from pad to function bit1
48 Bit#(1) output_en; // output enable from core to pad bit0
49 } FunctionType deriving(Eq,Bits,FShow);
50
51 typedef struct{
52 Bit#(1) outputval; // output from core to pad bit7
53 Bit#(1) output_en; // output enable from core to pad bit6
54 Bit#(1) input_en; // input enable from core to io_cell bit5
55 } GenericIOType deriving(Eq,Bits,FShow);
56
57 '''
58 footer = '''
59 endinterface;
60 endmodule
61 endpackage
62 '''
63
64
65 def pinmuxgen(pth=None, verify=True):
66 """ populating the file with the code
67 """
68
69 p = Parse(pth, verify)
70 ifaces = Interfaces(pth)
71 ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
72 init(p, ifaces)
73
74 bp = 'bsv_src'
75 if pth:
76 bp = os.path.join(pth, bp)
77 if not os.path.exists(bp):
78 os.makedirs(bp)
79 bl = os.path.join(bp, 'bsv_lib')
80 if not os.path.exists(bl):
81 os.makedirs(bl)
82
83 cwd = os.path.split(__file__)[0]
84
85 # copy over template and library files
86 shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
87 os.path.join(bp, 'Makefile'))
88 cwd = os.path.join(cwd, 'bsv_lib')
89 for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
90 shutil.copyfile(os.path.join(cwd, fname),
91 os.path.join(bl, fname))
92
93 bus = os.path.join(bp, 'busenable.bsv')
94 pmp = os.path.join(bp, 'pinmux.bsv')
95 ptp = os.path.join(bp, 'PinTop.bsv')
96 bvp = os.path.join(bp, 'bus.bsv')
97
98 write_pmp(pmp, p, ifaces)
99 write_ptp(ptp, p, ifaces)
100 write_bvp(bvp, p, ifaces)
101 write_bus(bus, p, ifaces)
102
103
104 def write_bus(bus, p, ifaces):
105 # package and interface declaration followed by
106 # the generic io_cell definition
107 with open(bus, "w") as bsv_file:
108 ifaces.busfmt(bsv_file)
109
110
111 def write_pmp(pmp, p, ifaces):
112 # package and interface declaration followed by
113 # the generic io_cell definition
114 with open(pmp, "w") as bsv_file:
115 bsv_file.write(header)
116
117 cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
118 bsv_file.write('''\
119 interface MuxSelectionLines;
120
121 // declare the method which will capture the user pin-mux
122 // selection values.The width of the input is dependent on the number
123 // of muxes happening per IO. For now we have a generalized width
124 // where each IO will have the same number of muxes.''')
125
126 for cell in p.muxed_cells:
127 bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
128
129 bsv_file.write('''
130 endinterface
131
132 interface PeripheralSide;
133 // declare the interface to the IO cells.
134 // Each IO cell will have 8 input field (output from pin mux
135 // and on output field (input to pinmux)''')
136 # ==============================================================
137
138 # == create method definitions for all peripheral interfaces ==#
139 ifaces.ifacefmt(bsv_file)
140
141 # ==============================================================
142
143 # ===== finish interface definition and start module definition=======
144 bsv_file.write('''
145 endinterface
146
147 interface Ifc_pinmux;
148 interface MuxSelectionLines mux_lines;
149 interface PeripheralSide peripheral_side;
150 endinterface
151 (*synthesize*)
152 module mkpinmux(Ifc_pinmux);
153 ''')
154 # ====================================================================
155
156 # ======================= create wire and registers =================#
157 bsv_file.write('''
158 // the followins wires capture the pin-mux selection
159 // values for each mux assigned to a CELL
160 ''')
161 for cell in p.muxed_cells:
162 bsv_file.write(mux_interface.wirefmt(
163 cell[0], cell_bit_width))
164
165 ifaces.wirefmt(bsv_file)
166
167 bsv_file.write("\n")
168 # ====================================================================
169 # ========================= Actual pinmuxing ========================#
170 bsv_file.write('''
171 /*====== This where the muxing starts for each io-cell======*/
172 ''')
173 bsv_file.write(p.pinmux)
174 bsv_file.write('''
175 /*============================================================*/
176 ''')
177 # ====================================================================
178 # ================= interface definitions for each method =============#
179 bsv_file.write('''
180 interface mux_lines = interface MuxSelectionLines
181 ''')
182 for cell in p.muxed_cells:
183 bsv_file.write(
184 mux_interface.ifacedef(
185 cell[0], cell_bit_width))
186 bsv_file.write('''
187 endinterface;
188 interface peripheral_side = interface PeripheralSide
189 ''')
190 ifaces.ifacedef(bsv_file)
191 bsv_file.write(footer)
192 print("BSV file successfully generated: bsv_src/pinmux.bsv")
193 # ======================================================================
194
195
196 def write_ptp(ptp, p, ifaces):
197 with open(ptp, 'w') as bsv_file:
198 bsv_file.write(copyright + '''
199 package PinTop;
200 import pinmux::*;
201 interface Ifc_PintTop;
202 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
203 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
204 interface PeripheralSide peripheral_side;
205 endinterface
206
207 module mkPinTop(Ifc_PintTop);
208 // instantiate the pin-mux module here
209 Ifc_pinmux pinmux <-mkpinmux;
210
211 // declare the registers which will be used to mux the IOs
212 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
213
214 cell_bit_width = str(p.cell_bitwidth)
215 for cell in p.muxed_cells:
216 bsv_file.write('''
217 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
218 cell_bit_width, cell[0]))
219
220 bsv_file.write('''
221 // rule to connect the registers to the selection lines of the
222 // pin-mux module
223 rule connect_selection_registers;''')
224
225 for cell in p.muxed_cells:
226 bsv_file.write('''
227 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
228
229 bsv_file.write('''
230 endrule
231 // method definitions for the write user interface
232 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
233 Bool err=False;
234 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
235 p.ADDR_WIDTH, p.DATA_WIDTH))
236 index = 0
237 for cell in p.muxed_cells:
238 bsv_file.write('''
239 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
240 index = index + 1
241
242 bsv_file.write('''
243 default: err=True;
244 endcase
245 return err;
246 endmethod''')
247
248 bsv_file.write('''
249 // method definitions for the read user interface
250 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
251 Bool err=False;
252 Bit#(32) data=0;
253 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
254 p.ADDR_WIDTH, p.DATA_WIDTH))
255 index = 0
256 for cell in p.muxed_cells:
257 bsv_file.write('''
258 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
259 index = index + 1
260
261 bsv_file.write('''
262 default:err=True;
263 endcase
264 return tuple2(err,data);
265 endmethod
266 interface peripheral_side=pinmux.peripheral_side;
267 endmodule
268 endpackage
269 ''')
270
271
272 def write_bvp(bvp, p, ifaces):
273 # ######## Generate bus transactors ################
274 with open(bvp, 'w') as bsv_file:
275 bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
276 # ##################################################