src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  90     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  91     soc = os.path.join(bp, 'socgen.bsv')
  92     soct = os.path.join(cwd, 'soc_template.bsv')
  93
  94     write_pmp(pmp, p, ifaces, iocells)
  95     write_ptp(ptp, p, ifaces)
  96     write_bvp(bvp, p, ifaces)
  97     write_bus(bus, p, ifaces)
  98     write_instances(idef, p, ifaces)
  99     write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
 100     write_soc(soc, soct, p, ifaces, iocells)
 101
 102
 103 def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
 104     """ write out the slow_peripherals.bsv file.
 105         joins all the peripherals together into one AXI Lite interface
 106     """
 107     with open(slowmt) as bsv_file:
 108         slowmt = bsv_file.read()
 109     with open(slowt) as bsv_file:
 110         slowt = bsv_file.read()
 111     imports = ifaces.slowimport()
 112     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 113     regdef = ifaces.axi_reg_def()
 114     slavedecl = ifaces.axi_slave_idx()
 115     fnaddrmap = ifaces.axi_addr_map()
 116     mkslow = ifaces.mkslow_peripheral()
 117     mkcon = ifaces.mk_connection()
 118     mkcellcon = ifaces.mk_cellconn()
 119     pincon = ifaces.mk_pincon()
 120     inst = ifaces.extifinstance()
 121     inst2 = ifaces.extifinstance2()
 122     mkplic = ifaces.mk_plic()
 123     numsloirqs = ifaces.mk_sloirqsdef()
 124     ifacedef = ifaces.mk_ext_ifacedef()
 125     ifacedef = ifaces.mk_ext_ifacedef()
 126
 127     with open(slow, "w") as bsv_file:
 128         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 129                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 130                                     pincon, inst, mkplic,
 131                                     numsloirqs, ifacedef,
 132                                     inst2))
 133
 134     with open(slowmf, "w") as bsv_file:
 135         bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
 136
 137
 138 def write_soc(soc, soct, p, ifaces, iocells):
 139     """ write out the soc.bsv file.
 140         joins all the peripherals together as AXI Masters
 141     """
 142     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 143     with open(soct) as bsv_file:
 144         soct = bsv_file.read()
 145     imports = ifaces.slowimport()
 146     ifdecl = ifaces.fastifdecl()
 147 #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 148     regdef = ifaces.axi_fastmem_def()
 149     slavedecl = ifaces.axi_fastslave_idx()
 150     mastdecl = ifaces.axi_master_idx()
 151     fnaddrmap = ifaces.axi_addr_map()
 152     mkfast = ifaces.mkfast_peripheral()
 153     mkcon = ifaces.mk_fast_connection()
 154     mkcellcon = ifaces.mk_cellconn()
 155     pincon = ifaces.mk_pincon()
 156     inst = ifaces.extfastifinstance()
 157     mkplic = ifaces.mk_plic()
 158     numsloirqs = ifaces.mk_sloirqsdef()
 159     ifacedef = ifaces.mk_ext_ifacedef()
 160     dma = ifaces.mk_dma_irq()
 161     num_dmachannels = ifaces.num_dmachannels()
 162     with open(soc, "w") as bsv_file:
 163         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 164                                    slavedecl, mastdecl, mkcon,
 165                                    inst, dma, num_dmachannels,
 166                                    pincon, regdef, fnaddrmap,
 167                                    ))
 168
 169
 170 def write_bus(bus, p, ifaces):
 171     # package and interface declaration followed by
 172     # the generic io_cell definition
 173     with open(bus, "w") as bsv_file:
 174         ifaces.busfmt(bsv_file)
 175
 176
 177 def write_pmp(pmp, p, ifaces, iocells):
 178     # package and interface declaration followed by
 179     # the generic io_cell definition
 180     with open(pmp, "w") as bsv_file:
 181         bsv_file.write(header)
 182
 183         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 184         bsv_file.write('''\
 185       (*always_ready,always_enabled*)
 186       interface MuxSelectionLines;
 187
 188       // declare the method which will capture the user pin-mux
 189       // selection values.The width of the input is dependent on the number
 190       // of muxes happening per IO. For now we have a generalized width
 191       // where each IO will have the same number of muxes.''')
 192
 193         for cell in p.muxed_cells:
 194             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 195
 196         bsv_file.write("\n      endinterface\n")
 197
 198         bsv_file.write('''
 199
 200       interface IOCellSide;
 201       // declare the interface to the IO cells.
 202       // Each IO cell will have 1 input field (output from pin mux)
 203       // and an output and out-enable field (input to pinmux)''')
 204
 205         # == create method definitions for all iocell interfaces ==#
 206         iocells.ifacefmt(bsv_file)
 207
 208         # ===== finish interface definition and start module definition=======
 209         bsv_file.write("\n      endinterface\n")
 210
 211         ifaces.ifacepfmt(bsv_file)
 212         # ===== io cell definition =======
 213         bsv_file.write('''
 214       (*always_ready,always_enabled*)
 215       interface PeripheralSide;
 216       // declare the interface to the peripherals
 217       // Each peripheral's function will be either an input, output
 218       // or be bi-directional.  an input field will be an output from the
 219       // peripheral and an output field will be an input to the peripheral.
 220       // Bi-directional functions also have an output-enable (which
 221       // again comes *in* from the peripheral)''')
 222         # ==============================================================
 223
 224         # == create method definitions for all peripheral interfaces ==#
 225         ifaces.ifacefmt2(bsv_file)
 226         bsv_file.write("\n      endinterface\n")
 227
 228         # ===== finish interface definition and start module definition=======
 229         bsv_file.write('''
 230
 231    interface Ifc_pinmux;
 232       // this interface controls how each IO cell is routed.  setting
 233       // any given IO cell's mux control value will result in redirection
 234       // of not just the input or output to different peripheral functions
 235       // but also the *direction* control - if appropriate - as well.
 236       interface MuxSelectionLines mux_lines;
 237
 238       // this interface contains the inputs, outputs and direction-control
 239       // lines for all peripherals.  GPIO is considered to also be just
 240       // a peripheral because it also has in, out and direction-control.
 241       interface PeripheralSide peripheral_side;
 242
 243       // this interface is to be linked to the individual IO cells.
 244       // if looking at a "non-muxed" GPIO design, basically the
 245       // IO cell input, output and direction-control wires are cut
 246       // (giving six pairs of dangling wires, named left and right)
 247       // these iocells are routed in their place on one side ("left")
 248       // and the matching *GPIO* peripheral interfaces in/out/dir
 249       // connect to the OTHER side ("right").  the result is that
 250       // the muxer settings end up controlling the routing of where
 251       // the I/O from the IOcell actually goes.
 252       interface IOCellSide iocell_side;
 253    endinterface
 254
 255    (*synthesize*)
 256    module mkpinmux(Ifc_pinmux);
 257 ''')
 258         # ====================================================================
 259
 260         # ======================= create wire and registers =================#
 261         bsv_file.write('''
 262       // the followins wires capture the pin-mux selection
 263       // values for each mux assigned to a CELL
 264 ''')
 265         for cell in p.muxed_cells:
 266             bsv_file.write(mux_interface.wirefmt(
 267                 cell[0], cell_bit_width))
 268
 269         iocells.wirefmt(bsv_file)
 270         ifaces.wirefmt(bsv_file)
 271
 272         bsv_file.write("\n")
 273         # ====================================================================
 274         # ========================= Actual pinmuxing ========================#
 275         bsv_file.write('''
 276       /*====== This where the muxing starts for each io-cell======*/
 277       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 278 ''')
 279         bsv_file.write(p.pinmux)
 280         bsv_file.write('''
 281       /*============================================================*/
 282 ''')
 283         # ====================================================================
 284         # ================= interface definitions for each method =============#
 285         bsv_file.write('''
 286     interface mux_lines = interface MuxSelectionLines
 287 ''')
 288         for cell in p.muxed_cells:
 289             bsv_file.write(
 290                 mux_interface.ifacedef(
 291                     cell[0], cell_bit_width))
 292         bsv_file.write("\n    endinterface;")
 293
 294         bsv_file.write('''
 295
 296     interface iocell_side = interface IOCellSide
 297 ''')
 298         iocells.ifacedef(bsv_file)
 299         bsv_file.write("\n     endinterface;")
 300
 301         bsv_file.write('''
 302
 303      interface peripheral_side = interface PeripheralSide
 304 ''')
 305         ifaces.ifacedef2(bsv_file)
 306         bsv_file.write("\n      endinterface;")
 307
 308         bsv_file.write(footer)
 309         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 310         # ======================================================================
 311
 312
 313 def write_ptp(ptp, p, ifaces):
 314     with open(ptp, 'w') as bsv_file:
 315         bsv_file.write(copyright + '''
 316 package PinTop;
 317     import pinmux::*;
 318     interface Ifc_PintTop;
 319         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 320         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 321         interface PeripheralSide peripheral_side;
 322     endinterface
 323
 324     module mkPinTop(Ifc_PintTop);
 325         // instantiate the pin-mux module here
 326         Ifc_pinmux pinmux <-mkpinmux;
 327
 328         // declare the registers which will be used to mux the IOs
 329 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 330
 331         cell_bit_width = str(p.cell_bitwidth)
 332         for cell in p.muxed_cells:
 333             bsv_file.write('''
 334                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 335                 cell_bit_width, cell[0]))
 336
 337         bsv_file.write('''
 338         // rule to connect the registers to the selection lines of the
 339         // pin-mux module
 340         rule connect_selection_registers;''')
 341
 342         for cell in p.muxed_cells:
 343             bsv_file.write('''
 344           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 345
 346         bsv_file.write('''
 347         endrule
 348         // method definitions for the write user interface
 349         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 350           Bool err=False;
 351           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 352                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 353         index = 0
 354         for cell in p.muxed_cells:
 355             bsv_file.write('''
 356             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 357             index = index + 1
 358
 359         bsv_file.write('''
 360             default: err=True;
 361           endcase
 362           return err;
 363         endmethod''')
 364
 365         bsv_file.write('''
 366         // method definitions for the read user interface
 367         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 368           Bool err=False;
 369           Bit#(32) data=0;
 370           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 371                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 372         index = 0
 373         for cell in p.muxed_cells:
 374             bsv_file.write('''
 375                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 376             index = index + 1
 377
 378         bsv_file.write('''
 379             default:err=True;
 380           endcase
 381           return tuple2(err,data);
 382         endmethod
 383         interface peripheral_side=pinmux.peripheral_side;
 384     endmodule
 385 endpackage
 386 ''')
 387
 388
 389 def write_bvp(bvp, p, ifaces):
 390     # ######## Generate bus transactors ################
 391     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 392               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 393     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 394         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 395
 396     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 397     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 398     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 399               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 400     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 401         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 402     with open(bvp, 'w') as bsv_file:
 403         # assume here that all muxes have a 1:1 gpio
 404         cfg = []
 405         decl = []
 406         idec = []
 407         iks = sorted(ifaces.keys())
 408         for iname in iks:
 409             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 410                 continue
 411             bank = iname[4:]
 412             ifc = ifaces[iname]
 413             npins = len(ifc.pinspecs)
 414             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 415                                       0,  # USERSPACE
 416                                       bank, npins))
 417             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 418                                      0,  # USERSPACE
 419                                      bank, npins))
 420             decl.append(gpiodec.format(npins, bank))
 421             decl.append(muxdec .format(npins, bank))
 422             idec.append(gpioifc.format(bank))
 423             idec.append(muxifc.format(bank))
 424         print dir(ifaces)
 425         print ifaces.items()
 426         print dir(ifaces['gpioa'])
 427         print ifaces['gpioa'].pinspecs
 428         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 429         gpiocfg = '\n'.join(cfg)
 430         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 431     # ##################################################
 432
 433
 434 def write_instances(idef, p, ifaces):
 435     with open(idef, 'w') as bsv_file:
 436         txt = '''\
 437 `define ADDR {0}
 438 `define PADDR {0}
 439 `define DATA {1}
 440 `define Reg_width {1}
 441 `define USERSPACE 0
 442 `define RV64
 443
 444 // TODO: work out if these are needed
 445 `define PWM_AXI4Lite
 446 `define PRFDEPTH 6
 447 `define VADDR 39
 448 `define DCACHE_BLOCK_SIZE 4
 449 `define DCACHE_WORD_SIZE 8
 450 `define PERFMONITORS                            64
 451 `define DCACHE_WAYS 4
 452 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 453
 454 // CLINT
 455     `define ClintBase       'h02000000
 456     `define ClintEnd        'h020BFFFF
 457
 458 `define PLIC
 459         `define PLICBase                'h0c000000
 460         `define PLICEnd         'h10000000
 461 `define INTERRUPT_PINS 64
 462
 463 `define BAUD_RATE 130
 464 `ifdef simulate
 465   `define BAUD_RATE 5 //130 //
 466 `endif
 467 '''
 468         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))