1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
25 # project module imports
26 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
27 from parse
import Parse
28 from bsv
.actual_pinmux
import init
29 from bsv
.bus_transactors
import axi4_lite
33 This BSV file has been generated by the PinMux tool available at:
34 https://bitbucket.org/casl/pinmux.
36 Authors: Neel Gala, Luke
37 Date of generation: ''' + time
.strftime("%c") + '''
40 header
= copyright
+ '''
44 Bit#(1) outputval; // output from core to pad bit7
45 Bit#(1) output_en; // output enable from core to pad bit6
46 Bit#(1) input_en; // input enable from core to io_cell bit5
47 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
48 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
49 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
50 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
51 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
52 } GenericIOType deriving(Eq,Bits,FShow);
62 def pinmuxgen(pth
=None, verify
=True):
63 """ populating the file with the code
66 p
= Parse(pth
, verify
)
67 ifaces
= Interfaces(pth
)
68 ifaces
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
73 bp
= os
.path
.join(pth
, bp
)
74 if not os
.path
.exists(bp
):
76 bl
= os
.path
.join(bp
, 'bsv_lib')
77 if not os
.path
.exists(bl
):
80 cwd
= os
.path
.split(__file__
)[0]
82 # copy over template and library files
83 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
84 os
.path
.join(bp
, 'Makefile'))
85 cwd
= os
.path
.join(cwd
, 'bsv_lib')
86 for fname
in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
87 shutil
.copyfile(os
.path
.join(cwd
, fname
),
88 os
.path
.join(bl
, fname
))
90 bus
= os
.path
.join(bp
, 'busenable.bsv')
91 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
92 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
93 bvp
= os
.path
.join(bp
, 'bus.bsv')
95 write_pmp(pmp
, p
, ifaces
)
96 write_ptp(ptp
, p
, ifaces
)
97 write_bvp(bvp
, p
, ifaces
)
98 write_bus(bus
, p
, ifaces
)
101 def write_bus(bus
, p
, ifaces
):
102 # package and interface declaration followed by
103 # the generic io_cell definition
104 with
open(bus
, "w") as bsv_file
:
105 ifaces
.busfmt(bsv_file
)
108 def get_cell_bit_width(p
):
110 for cell
in p
.muxed_cells
:
111 max_num_cells
= max(len(cell
) - 1, max_num_cells
)
112 return int(math
.log(max_num_cells
, 2))
115 def write_pmp(pmp
, p
, ifaces
):
116 # package and interface declaration followed by
117 # the generic io_cell definition
118 with
open(pmp
, "w") as bsv_file
:
119 bsv_file
.write(header
)
122 interface MuxSelectionLines;
124 // declare the method which will capture the user pin-mux
125 // selection values.The width of the input is dependent on the number
126 // of muxes happening per IO. For now we have a generalized width
127 // where each IO will have the same number of muxes.''')
129 for cell
in p
.muxed_cells
:
130 cnum
= 'Bit#(' + str(int(math
.log(len(cell
) - 1, 2))) + ')'
131 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cnum
))
136 interface PeripheralSide;
137 // declare the interface to the IO cells.
138 // Each IO cell will have 8 input field (output from pin mux
139 // and on output field (input to pinmux)''')
140 # ==============================================================
142 # == create method definitions for all peripheral interfaces ==#
143 ifaces
.ifacefmt(bsv_file
)
145 # ==============================================================
147 # ===== finish interface definition and start module definition=======
151 interface Ifc_pinmux;
152 interface MuxSelectionLines mux_lines;
153 interface PeripheralSide peripheral_side;
156 module mkpinmux(Ifc_pinmux);
158 # ====================================================================
160 # ======================= create wire and registers =================#
162 // the followins wires capture the pin-mux selection
163 // values for each mux assigned to a CELL
165 cell_bit_width
= 'Bit#(%d)' % get_cell_bit_width(p
)
166 for cell
in p
.muxed_cells
:
167 bsv_file
.write(mux_interface
.wirefmt(
168 cell
[0], cell_bit_width
))
170 ifaces
.wirefmt(bsv_file
)
173 # ====================================================================
174 # ========================= Actual pinmuxing ========================#
176 /*====== This where the muxing starts for each io-cell======*/
178 bsv_file
.write(p
.pinmux
)
180 /*============================================================*/
182 # ====================================================================
183 # ================= interface definitions for each method =============#
185 interface mux_lines = interface MuxSelectionLines
187 for cell
in p
.muxed_cells
:
189 mux_interface
.ifacedef(
190 cell
[0], cell_bit_width
))
193 interface peripheral_side = interface PeripheralSide
195 ifaces
.ifacedef(bsv_file
)
196 bsv_file
.write(footer
)
197 print("BSV file successfully generated: bsv_src/pinmux.bsv")
198 # ======================================================================
201 def write_ptp(ptp
, p
, ifaces
):
202 with
open(ptp
, 'w') as bsv_file
:
203 bsv_file
.write(copyright
+ '''
206 interface Ifc_PintTop;
207 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
208 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
209 interface PeripheralSide peripheral_side;
212 module mkPinTop(Ifc_PintTop);
213 // instantiate the pin-mux module here
214 Ifc_pinmux pinmux <-mkpinmux;
216 // declare the registers which will be used to mux the IOs
217 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
219 cell_bit_width
= str(get_cell_bit_width(p
))
220 for cell
in p
.muxed_cells
:
222 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
223 cell_bit_width
, cell
[0]))
226 // rule to connect the registers to the selection lines of the
228 rule connect_selection_registers;''')
230 for cell
in p
.muxed_cells
:
232 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
236 // method definitions for the write user interface
237 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
239 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
240 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
242 for cell
in p
.muxed_cells
:
244 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
254 // method definitions for the read user interface
255 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
258 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
259 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
261 for cell
in p
.muxed_cells
:
263 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
269 return tuple2(err,data);
271 interface peripheral_side=pinmux.peripheral_side;
277 def write_bvp(bvp
, p
, ifaces
):
278 # ######## Generate bus transactors ################
279 with
open(bvp
, 'w') as bsv_file
:
280 bsv_file
.write(axi4_lite
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
281 # ##################################################