src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89
  90     write_pmp(pmp, p, ifaces, iocells)
  91     write_ptp(ptp, p, ifaces)
  92     write_bvp(bvp, p, ifaces)
  93     write_bus(bus, p, ifaces)
  94     write_instances(idef, p, ifaces)
  95     write_slow(slow, slowt, p, ifaces, iocells)
  96
  97
  98 def write_slow(slow, slowt, p, ifaces, iocells):
  99     """ write out the slow_peripherals.bsv file.
 100         joins all the peripherals together into one AXI Lite interface
 101     """
 102     with open(slowt) as bsv_file:
 103         slowt = bsv_file.read()
 104     imports = ifaces.slowimport()
 105     ifdecl = ifaces.slowifdeclmux()
 106     regdef = ifaces.axi_reg_def()
 107     slavedecl = ifaces.axi_slave_idx()
 108     fnaddrmap = ifaces.axi_addr_map()
 109     mkslow = ifaces.mkslow_peripheral()
 110     mkcon = ifaces.mk_connection()
 111     mkcellcon = ifaces.mk_cellconn()
 112     pincon = ifaces.mk_pincon()
 113     inst = ifaces.extifinstance()
 114     mkplic = ifaces.mk_plic()
 115     numsloirqs = ifaces.mk_sloirqsdef()
 116     ifacedef = ifaces.mk_ext_ifacedef()
 117     ifacedef = ifaces.mk_ext_ifacedef()
 118     with open(slow, "w") as bsv_file:
 119         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 120                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 121                                     pincon, inst, mkplic,
 122                                     numsloirqs, ifacedef))
 123
 124
 125 def write_bus(bus, p, ifaces):
 126     # package and interface declaration followed by
 127     # the generic io_cell definition
 128     with open(bus, "w") as bsv_file:
 129         ifaces.busfmt(bsv_file)
 130
 131
 132 def write_pmp(pmp, p, ifaces, iocells):
 133     # package and interface declaration followed by
 134     # the generic io_cell definition
 135     with open(pmp, "w") as bsv_file:
 136         bsv_file.write(header)
 137
 138         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 139         bsv_file.write('''\
 140       (*always_ready,always_enabled*)
 141       interface MuxSelectionLines;
 142
 143       // declare the method which will capture the user pin-mux
 144       // selection values.The width of the input is dependent on the number
 145       // of muxes happening per IO. For now we have a generalized width
 146       // where each IO will have the same number of muxes.''')
 147
 148         for cell in p.muxed_cells:
 149             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 150
 151         bsv_file.write("\n      endinterface\n")
 152
 153         bsv_file.write('''
 154
 155       interface IOCellSide;
 156       // declare the interface to the IO cells.
 157       // Each IO cell will have 1 input field (output from pin mux)
 158       // and an output and out-enable field (input to pinmux)''')
 159
 160         # == create method definitions for all iocell interfaces ==#
 161         iocells.ifacefmt(bsv_file)
 162
 163         # ===== finish interface definition and start module definition=======
 164         bsv_file.write("\n      endinterface\n")
 165
 166         ifaces.ifacepfmt(bsv_file)
 167         # ===== io cell definition =======
 168         bsv_file.write('''
 169       (*always_ready,always_enabled*)
 170       interface PeripheralSide;
 171       // declare the interface to the peripherals
 172       // Each peripheral's function will be either an input, output
 173       // or be bi-directional.  an input field will be an output from the
 174       // peripheral and an output field will be an input to the peripheral.
 175       // Bi-directional functions also have an output-enable (which
 176       // again comes *in* from the peripheral)''')
 177         # ==============================================================
 178
 179         # == create method definitions for all peripheral interfaces ==#
 180         ifaces.ifacefmt2(bsv_file)
 181         bsv_file.write("\n      endinterface\n")
 182
 183         # ===== finish interface definition and start module definition=======
 184         bsv_file.write('''
 185
 186    interface Ifc_pinmux;
 187       // this interface controls how each IO cell is routed.  setting
 188       // any given IO cell's mux control value will result in redirection
 189       // of not just the input or output to different peripheral functions
 190       // but also the *direction* control - if appropriate - as well.
 191       interface MuxSelectionLines mux_lines;
 192
 193       // this interface contains the inputs, outputs and direction-control
 194       // lines for all peripherals.  GPIO is considered to also be just
 195       // a peripheral because it also has in, out and direction-control.
 196       interface PeripheralSide peripheral_side;
 197
 198       // this interface is to be linked to the individual IO cells.
 199       // if looking at a "non-muxed" GPIO design, basically the
 200       // IO cell input, output and direction-control wires are cut
 201       // (giving six pairs of dangling wires, named left and right)
 202       // these iocells are routed in their place on one side ("left")
 203       // and the matching *GPIO* peripheral interfaces in/out/dir
 204       // connect to the OTHER side ("right").  the result is that
 205       // the muxer settings end up controlling the routing of where
 206       // the I/O from the IOcell actually goes.
 207       interface IOCellSide iocell_side;
 208    endinterface
 209
 210    (*synthesize*)
 211    module mkpinmux(Ifc_pinmux);
 212 ''')
 213         # ====================================================================
 214
 215         # ======================= create wire and registers =================#
 216         bsv_file.write('''
 217       // the followins wires capture the pin-mux selection
 218       // values for each mux assigned to a CELL
 219 ''')
 220         for cell in p.muxed_cells:
 221             bsv_file.write(mux_interface.wirefmt(
 222                 cell[0], cell_bit_width))
 223
 224         iocells.wirefmt(bsv_file)
 225         ifaces.wirefmt(bsv_file)
 226
 227         bsv_file.write("\n")
 228         # ====================================================================
 229         # ========================= Actual pinmuxing ========================#
 230         bsv_file.write('''
 231       /*====== This where the muxing starts for each io-cell======*/
 232       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 233 ''')
 234         bsv_file.write(p.pinmux)
 235         bsv_file.write('''
 236       /*============================================================*/
 237 ''')
 238         # ====================================================================
 239         # ================= interface definitions for each method =============#
 240         bsv_file.write('''
 241     interface mux_lines = interface MuxSelectionLines
 242 ''')
 243         for cell in p.muxed_cells:
 244             bsv_file.write(
 245                 mux_interface.ifacedef(
 246                     cell[0], cell_bit_width))
 247         bsv_file.write("\n    endinterface;")
 248
 249         bsv_file.write('''
 250
 251     interface iocell_side = interface IOCellSide
 252 ''')
 253         iocells.ifacedef(bsv_file)
 254         bsv_file.write("\n     endinterface;")
 255
 256         bsv_file.write('''
 257
 258      interface peripheral_side = interface PeripheralSide
 259 ''')
 260         ifaces.ifacedef2(bsv_file)
 261         bsv_file.write("\n      endinterface;")
 262
 263         bsv_file.write(footer)
 264         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 265         # ======================================================================
 266
 267
 268 def write_ptp(ptp, p, ifaces):
 269     with open(ptp, 'w') as bsv_file:
 270         bsv_file.write(copyright + '''
 271 package PinTop;
 272     import pinmux::*;
 273     interface Ifc_PintTop;
 274         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 275         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 276         interface PeripheralSide peripheral_side;
 277     endinterface
 278
 279     module mkPinTop(Ifc_PintTop);
 280         // instantiate the pin-mux module here
 281         Ifc_pinmux pinmux <-mkpinmux;
 282
 283         // declare the registers which will be used to mux the IOs
 284 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 285
 286         cell_bit_width = str(p.cell_bitwidth)
 287         for cell in p.muxed_cells:
 288             bsv_file.write('''
 289                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 290                 cell_bit_width, cell[0]))
 291
 292         bsv_file.write('''
 293         // rule to connect the registers to the selection lines of the
 294         // pin-mux module
 295         rule connect_selection_registers;''')
 296
 297         for cell in p.muxed_cells:
 298             bsv_file.write('''
 299           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 300
 301         bsv_file.write('''
 302         endrule
 303         // method definitions for the write user interface
 304         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 305           Bool err=False;
 306           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 307                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 308         index = 0
 309         for cell in p.muxed_cells:
 310             bsv_file.write('''
 311             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 312             index = index + 1
 313
 314         bsv_file.write('''
 315             default: err=True;
 316           endcase
 317           return err;
 318         endmethod''')
 319
 320         bsv_file.write('''
 321         // method definitions for the read user interface
 322         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 323           Bool err=False;
 324           Bit#(32) data=0;
 325           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 326                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 327         index = 0
 328         for cell in p.muxed_cells:
 329             bsv_file.write('''
 330                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 331             index = index + 1
 332
 333         bsv_file.write('''
 334             default:err=True;
 335           endcase
 336           return tuple2(err,data);
 337         endmethod
 338         interface peripheral_side=pinmux.peripheral_side;
 339     endmodule
 340 endpackage
 341 ''')
 342
 343
 344 def write_bvp(bvp, p, ifaces):
 345     # ######## Generate bus transactors ################
 346     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 347               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 348     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 349         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 350
 351     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 352     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 353     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 354               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 355     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 356         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 357     with open(bvp, 'w') as bsv_file:
 358         # assume here that all muxes have a 1:1 gpio
 359         cfg = []
 360         decl = []
 361         idec = []
 362         iks = sorted(ifaces.keys())
 363         for iname in iks:
 364             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 365                 continue
 366             bank = iname[4:]
 367             ifc = ifaces[iname]
 368             npins = len(ifc.pinspecs)
 369             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 370                                       0,  # USERSPACE
 371                                       bank, npins))
 372             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 373                                      0,  # USERSPACE
 374                                      bank, npins))
 375             decl.append(gpiodec.format(npins, bank))
 376             decl.append(muxdec .format(npins, bank))
 377             idec.append(gpioifc.format(bank))
 378             idec.append(muxifc.format(bank))
 379         print dir(ifaces)
 380         print ifaces.items()
 381         print dir(ifaces['gpioa'])
 382         print ifaces['gpioa'].pinspecs
 383         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 384         gpiocfg = '\n'.join(cfg)
 385         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 386     # ##################################################
 387
 388
 389 def write_instances(idef, p, ifaces):
 390     with open(idef, 'w') as bsv_file:
 391         txt = '''\
 392 `define ADDR {0}
 393 `define PADDR {0}
 394 `define DATA {1}
 395 `define Reg_width {1}
 396 `define USERSPACE 0
 397
 398 // TODO: work out if these are needed
 399 `define PWM_AXI4Lite
 400 `define PRFDEPTH 6
 401 `define VADDR 39
 402 `define DCACHE_BLOCK_SIZE 4
 403 `define DCACHE_WORD_SIZE 8
 404 `define PERFMONITORS                            64
 405 `define DCACHE_WAYS 4
 406 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 407 `define PLIC
 408         `define PLICBase                'h0c000000
 409         `define PLICEnd         'h10000000
 410 `define INTERRUPT_PINS 64
 411
 412 `define BAUD_RATE 130
 413 `ifdef simulate
 414   `define BAUD_RATE 5 //130 //
 415 `endif
 416 '''
 417         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))