src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23 import math
  24
  25 # project module imports
  26 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  27 from parse import Parse
  28 from bsv.actual_pinmux import init
  29 from bsv.bus_transactors import axi4_lite
  30
  31 copyright = '''
  32 /*
  33    This BSV file has been generated by the PinMux tool available at:
  34    https://bitbucket.org/casl/pinmux.
  35
  36    Authors: Neel Gala, Luke
  37    Date of generation: ''' + time.strftime("%c") + '''
  38 */
  39 '''
  40 header = copyright + '''
  41 package pinmux;
  42
  43    // FunctionType: contains the active wires of a function.  That INCLUDES
  44    // GPIO (as GPIO is also a "Function").  These are what get muxed.
  45    // However, only GPIO "Functions" will end up with Register SRAMs.
  46    typedef struct{
  47       Bit#(1) outputval;      // output from function to pad            bit2
  48       Bit#(1) inputval;       // input  from pad to function            bit1
  49       Bit#(1) output_en;      // output enable from core to pad         bit0
  50    } FunctionType deriving(Eq,Bits,FShow);
  51
  52    // PadCharacteristicsType: this is the controllable characteristics
  53    // of the I/O cell.  They are NOT multiplexed.  Registers are to be
  54    // created which manage these characteristics
  55    typedef struct{
  56       Bit#(1) pullup_en;      // pullup enable from core to io_cell     bit4
  57       Bit#(1) pulldown_en;    // pulldown enable from core to io_cell   bit3
  58       Bit#(1) drivestrength;  // drivestrength from core to io_cell     bit2
  59       Bit#(1) pushpull_en;    // pushpull enable from core to io_cell   bit1
  60       Bit#(1) opendrain_en;   // opendrain enable form core to io_cell  bit0
  61    } PadCharacteristicsType deriving(Eq,Bits,FShow);
  62
  63    // TODO: leave this in for now, needs replacing with the above
  64    typedef struct{
  65       Bit#(1) outputval;      // output from core to pad                bit7
  66       Bit#(1) output_en;      // output enable from core to pad         bit6
  67       Bit#(1) input_en;       // input enable from core to io_cell      bit5
  68       Bit#(1) pullup_en;      // pullup enable from core to io_cell     bit4
  69       Bit#(1) pulldown_en;    // pulldown enable from core to io_cell   bit3
  70       Bit#(1) drivestrength;  // drivestrength from core to io_cell     bit2
  71       Bit#(1) pushpull_en;    // pushpull enable from core to io_cell   bit1
  72       Bit#(1) opendrain_en;   // opendrain enable form core to io_cell  bit0
  73    } GenericIOType deriving(Eq,Bits,FShow);
  74
  75 '''
  76 footer = '''
  77      endinterface;
  78    endmodule
  79 endpackage
  80 '''
  81
  82
  83 def pinmuxgen(pth=None, verify=True):
  84     """ populating the file with the code
  85     """
  86
  87     p = Parse(pth, verify)
  88     ifaces = Interfaces(pth)
  89     ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  90     init(p, ifaces)
  91
  92     bp = 'bsv_src'
  93     if pth:
  94         bp = os.path.join(pth, bp)
  95     if not os.path.exists(bp):
  96         os.makedirs(bp)
  97     bl = os.path.join(bp, 'bsv_lib')
  98     if not os.path.exists(bl):
  99         os.makedirs(bl)
 100
 101     cwd = os.path.split(__file__)[0]
 102
 103     # copy over template and library files
 104     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
 105                     os.path.join(bp, 'Makefile'))
 106     cwd = os.path.join(cwd, 'bsv_lib')
 107     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
 108         shutil.copyfile(os.path.join(cwd, fname),
 109                         os.path.join(bl, fname))
 110
 111     bus = os.path.join(bp, 'busenable.bsv')
 112     pmp = os.path.join(bp, 'pinmux.bsv')
 113     ptp = os.path.join(bp, 'PinTop.bsv')
 114     bvp = os.path.join(bp, 'bus.bsv')
 115
 116     write_pmp(pmp, p, ifaces)
 117     write_ptp(ptp, p, ifaces)
 118     write_bvp(bvp, p, ifaces)
 119     write_bus(bus, p, ifaces)
 120
 121
 122 def write_bus(bus, p, ifaces):
 123     # package and interface declaration followed by
 124     # the generic io_cell definition
 125     with open(bus, "w") as bsv_file:
 126         ifaces.busfmt(bsv_file)
 127
 128
 129 def get_cell_bit_width(p):
 130     max_num_cells = 0
 131     for cell in p.muxed_cells:
 132         max_num_cells = max(len(cell) - 1, max_num_cells)
 133     return int(math.log(max_num_cells, 2))
 134
 135
 136 def write_pmp(pmp, p, ifaces):
 137     # package and interface declaration followed by
 138     # the generic io_cell definition
 139     with open(pmp, "w") as bsv_file:
 140         bsv_file.write(header)
 141
 142         bsv_file.write('''\
 143    interface MuxSelectionLines;
 144
 145       // declare the method which will capture the user pin-mux
 146       // selection values.The width of the input is dependent on the number
 147       // of muxes happening per IO. For now we have a generalized width
 148       // where each IO will have the same number of muxes.''')
 149
 150         for cell in p.muxed_cells:
 151             cnum = 'Bit#(' + str(int(math.log(len(cell) - 1, 2))) + ')'
 152             bsv_file.write(mux_interface.ifacefmt(cell[0], cnum))
 153
 154         bsv_file.write('''
 155       endinterface
 156
 157       interface PeripheralSide;
 158       // declare the interface to the IO cells.
 159       // Each IO cell will have 8 input field (output from pin mux
 160       // and on output field (input to pinmux)''')
 161         # ==============================================================
 162
 163         # == create method definitions for all peripheral interfaces ==#
 164         ifaces.ifacefmt(bsv_file)
 165
 166         # ==============================================================
 167
 168         # ===== finish interface definition and start module definition=======
 169         bsv_file.write('''
 170    endinterface
 171
 172    interface Ifc_pinmux;
 173       interface MuxSelectionLines mux_lines;
 174       interface PeripheralSide peripheral_side;
 175    endinterface
 176    (*synthesize*)
 177    module mkpinmux(Ifc_pinmux);
 178 ''')
 179         # ====================================================================
 180
 181         # ======================= create wire and registers =================#
 182         bsv_file.write('''
 183       // the followins wires capture the pin-mux selection
 184       // values for each mux assigned to a CELL
 185 ''')
 186         cell_bit_width = 'Bit#(%d)' % get_cell_bit_width(p)
 187         for cell in p.muxed_cells:
 188             bsv_file.write(mux_interface.wirefmt(
 189                 cell[0], cell_bit_width))
 190
 191         ifaces.wirefmt(bsv_file)
 192
 193         bsv_file.write("\n")
 194         # ====================================================================
 195         # ========================= Actual pinmuxing ========================#
 196         bsv_file.write('''
 197       /*====== This where the muxing starts for each io-cell======*/
 198 ''')
 199         bsv_file.write(p.pinmux)
 200         bsv_file.write('''
 201       /*============================================================*/
 202 ''')
 203         # ====================================================================
 204         # ================= interface definitions for each method =============#
 205         bsv_file.write('''
 206     interface mux_lines = interface MuxSelectionLines
 207 ''')
 208         for cell in p.muxed_cells:
 209             bsv_file.write(
 210                 mux_interface.ifacedef(
 211                     cell[0], cell_bit_width))
 212         bsv_file.write('''
 213     endinterface;
 214     interface peripheral_side = interface PeripheralSide
 215 ''')
 216         ifaces.ifacedef(bsv_file)
 217         bsv_file.write(footer)
 218         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 219         # ======================================================================
 220
 221
 222 def write_ptp(ptp, p, ifaces):
 223     with open(ptp, 'w') as bsv_file:
 224         bsv_file.write(copyright + '''
 225 package PinTop;
 226     import pinmux::*;
 227     interface Ifc_PintTop;
 228         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 229         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 230         interface PeripheralSide peripheral_side;
 231     endinterface
 232
 233     module mkPinTop(Ifc_PintTop);
 234         // instantiate the pin-mux module here
 235         Ifc_pinmux pinmux <-mkpinmux;
 236
 237         // declare the registers which will be used to mux the IOs
 238 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 239
 240         cell_bit_width = str(get_cell_bit_width(p))
 241         for cell in p.muxed_cells:
 242             bsv_file.write('''
 243                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 244                 cell_bit_width, cell[0]))
 245
 246         bsv_file.write('''
 247         // rule to connect the registers to the selection lines of the
 248         // pin-mux module
 249         rule connect_selection_registers;''')
 250
 251         for cell in p.muxed_cells:
 252             bsv_file.write('''
 253           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 254
 255         bsv_file.write('''
 256         endrule
 257         // method definitions for the write user interface
 258         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 259           Bool err=False;
 260           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 261                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 262         index = 0
 263         for cell in p.muxed_cells:
 264             bsv_file.write('''
 265             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 266             index = index + 1
 267
 268         bsv_file.write('''
 269             default: err=True;
 270           endcase
 271           return err;
 272         endmethod''')
 273
 274         bsv_file.write('''
 275         // method definitions for the read user interface
 276         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 277           Bool err=False;
 278           Bit#(32) data=0;
 279           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 280                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 281         index = 0
 282         for cell in p.muxed_cells:
 283             bsv_file.write('''
 284                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 285             index = index + 1
 286
 287         bsv_file.write('''
 288             default:err=True;
 289           endcase
 290           return tuple2(err,data);
 291         endmethod
 292         interface peripheral_side=pinmux.peripheral_side;
 293     endmodule
 294 endpackage
 295 ''')
 296
 297
 298 def write_bvp(bvp, p, ifaces):
 299     # ######## Generate bus transactors ################
 300     with open(bvp, 'w') as bsv_file:
 301         bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 302     # ##################################################