pep8, whitespace cleanup
[pinmux.git] / src / bsv / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import os
20 import os.path
21 import time
22 import math
23
24 # project module imports
25 from interface_decl import Interfaces, mux_interface, io_interface
26 from parse import Parse
27 from actual_pinmux import init
28 from bus_transactors import axi4_lite
29
30 copyright = '''
31 /*
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
34
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time.strftime("%c") + '''
37 */
38 '''
39 header = copyright + '''
40 package pinmux;
41
42 typedef struct{
43 Bit#(1) outputval; // output from core to pad bit7
44 Bit#(1) output_en; // output enable from core to pad bit6
45 Bit#(1) input_en; // input enable from core to io_cell bit5
46 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
47 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
48 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
49 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
50 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
51 } GenericIOType deriving(Eq,Bits,FShow);
52
53 '''
54 footer = '''
55 endinterface;
56 endmodule
57 endpackage
58 '''
59
60
61 def pinmuxgen(pth=None, verify=True):
62 """ populating the file with the code
63 """
64
65 p = Parse(pth, verify)
66 init(p)
67 ifaces = Interfaces(pth)
68 ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
69
70 bp = 'bsv_src'
71 if pth:
72 bp = os.path.join(pth, bp)
73 if not os.path.exists(bp):
74 os.makedirs(bp)
75
76 pmp = os.path.join(bp, 'pinmux.bsv')
77 ptp = os.path.join(bp, 'PinTop.bsv')
78 bvp = os.path.join(bp, 'bus.bsv')
79
80 # package and interface declaration followed by
81 # the generic io_cell definition
82 with open(pmp, "w") as bsv_file:
83 bsv_file.write(header)
84
85 bsv_file.write('''\
86 interface MuxSelectionLines;
87
88 // declare the method which will capture the user pin-mux
89 // selection values.The width of the input is dependent on the number
90 // of muxes happening per IO. For now we have a generalized width
91 // where each IO will have the same number of muxes.''')
92
93 for cell in p.muxed_cells:
94 cnum = int(math.log(len(cell) - 1, 2))
95 bsv_file.write(mux_interface.ifacefmt(cell[0], cnum))
96
97 bsv_file.write('''
98 endinterface
99
100 interface PeripheralSide;
101 // declare the interface to the IO cells.
102 // Each IO cell will have 8 input field (output from pin mux
103 // and on output field (input to pinmux)''')
104 # ==============================================================
105
106 # == create method definitions for all peripheral interfaces ==#
107 ifaces.ifacefmt(bsv_file)
108
109 # ==============================================================
110
111 # ===== finish interface definition and start module definition=======
112 bsv_file.write('''
113 endinterface
114
115 interface Ifc_pinmux;
116 interface MuxSelectionLines mux_lines;
117 interface PeripheralSide peripheral_side;
118 endinterface
119 (*synthesize*)
120 module mkpinmux(Ifc_pinmux);
121 ''')
122 # ====================================================================
123
124 # ======================= create wire and registers =================#
125 bsv_file.write('''
126 // the followins wires capture the pin-mux selection
127 // values for each mux assigned to a CELL
128 ''')
129 for cell in p.muxed_cells:
130 bsv_file.write(mux_interface.wirefmt(
131 cell[0], int(math.log(len(cell) - 1, 2))))
132
133 ifaces.wirefmt(bsv_file)
134
135 bsv_file.write("\n")
136 # ====================================================================
137 # ========================= Actual pinmuxing ========================#
138 bsv_file.write('''
139 /*====== This where the muxing starts for each io-cell======*/
140 ''')
141 bsv_file.write(p.pinmux)
142 bsv_file.write('''
143 /*============================================================*/
144 ''')
145 # ====================================================================
146 # ================= interface definitions for each method =============#
147 bsv_file.write('''
148 interface mux_lines = interface MuxSelectionLines
149 ''')
150 for cell in p.muxed_cells:
151 bsv_file.write(mux_interface.ifacedef(cell[0],
152 int(math.log(len(cell) - 1, 2))))
153 bsv_file.write('''
154 endinterface;
155 interface peripheral_side = interface PeripheralSide
156 ''')
157 ifaces.ifacedef(bsv_file)
158 bsv_file.write(footer)
159 print("BSV file successfully generated: bsv_src/pinmux.bsv")
160 # ======================================================================
161
162 with open(ptp, 'w') as bsv_file:
163 bsv_file.write(copyright + '''
164 package PinTop;
165 import pinmux::*;
166 interface Ifc_PintTop;
167 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
168 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
169 interface PeripheralSide peripheral_side;
170 endinterface
171
172 module mkPinTop(Ifc_PintTop);
173 // instantiate the pin-mux module here
174 Ifc_pinmux pinmux <-mkpinmux;
175
176 // declare the registers which will be used to mux the IOs
177 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
178
179 for cell in p.muxed_cells:
180 bsv_file.write('''
181 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
182 int(math.log(len(cell) - 1, 2)), cell[0]))
183
184 bsv_file.write('''
185 // rule to connect the registers to the selection lines of the
186 // pin-mux module
187 rule connect_selection_registers;''')
188
189 for cell in p.muxed_cells:
190 bsv_file.write('''
191 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
192
193 bsv_file.write('''
194 endrule
195 // method definitions for the write user interface
196 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
197 Bool err=False;
198 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
199 p.ADDR_WIDTH, p.DATA_WIDTH))
200 index = 0
201 for cell in p.muxed_cells:
202 bsv_file.write('''
203 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
204 index = index + 1
205
206 bsv_file.write('''
207 default: err=True;
208 endcase
209 return err;
210 endmethod''')
211
212 bsv_file.write('''
213 // method definitions for the read user interface
214 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
215 Bool err=False;
216 Bit#(32) data=0;
217 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
218 p.ADDR_WIDTH, p.DATA_WIDTH))
219 index = 0
220 for cell in p.muxed_cells:
221 bsv_file.write('''
222 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
223 index = index + 1
224
225 bsv_file.write('''
226 default:err=True;
227 endcase
228 return tuple2(err,data);
229 endmethod
230 interface peripheral_side=pinmux.peripheral_side;
231 endmodule
232 endpackage
233 ''')
234
235 # ######## Generate bus transactors ################
236 with open(bvp, 'w') as bsv_file:
237 bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
238 # ##################################################