src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  90     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  91     fastmf = os.path.join(bp, 'fast_memory_map.bsv')
  92     fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
  93     soc = os.path.join(bp, 'socgen.bsv')
  94     soct = os.path.join(cwd, 'soc_template.bsv')
  95
  96     write_pmp(pmp, p, ifaces, iocells)
  97     write_ptp(ptp, p, ifaces)
  98     write_bvp(bvp, p, ifaces)
  99     write_bus(bus, p, ifaces)
 100     write_instances(idef, p, ifaces)
 101     write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
 102     write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells)
 103
 104
 105 def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
 106     """ write out the slow_peripherals.bsv file.
 107         joins all the peripherals together into one AXI Lite interface
 108     """
 109     imports = ifaces.slowimport()
 110     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 111     regdef = ifaces.axi_reg_def()
 112     slavedecl = ifaces.axi_slave_idx()
 113     fnaddrmap = ifaces.axi_addr_map()
 114     mkslow = ifaces.mkslow_peripheral()
 115     mkcon = ifaces.mk_connection()
 116     mkcellcon = ifaces.mk_cellconn()
 117     pincon = ifaces.mk_pincon()
 118     inst = ifaces.extifinstance()
 119     inst2 = ifaces.extifinstance2()
 120     mkplic = ifaces.mk_plic()
 121     numsloirqs = ifaces.mk_sloirqsdef()
 122     ifacedef = ifaces.mk_ext_ifacedef()
 123     ifacedef = ifaces.mk_ext_ifacedef()
 124
 125     with open(slow, "w") as bsv_file:
 126         with open(slowt) as f:
 127             slowt = f.read()
 128         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 129                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 130                                     pincon, inst, mkplic,
 131                                     numsloirqs, ifacedef,
 132                                     inst2))
 133
 134     with open(slowmf, "w") as bsv_file:
 135         with open(slowmt) as f:
 136             slowmt = f.read()
 137         bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
 138
 139
 140 def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells):
 141     """ write out the soc.bsv file.
 142         joins all the peripherals together as AXI Masters
 143     """
 144     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 145
 146     imports = ifaces.slowimport()
 147     ifdecl = ifaces.fastifdecl()
 148     regdef = ifaces.axi_fastmem_def()
 149     slavedecl = ifaces.axi_fastslave_idx()
 150     mastdecl = ifaces.axi_master_idx()
 151     fnaddrmap = ifaces.axi_fastaddr_map()
 152     mkfast = ifaces.mkfast_peripheral()
 153     mkcon = ifaces.mk_fast_connection()
 154     mkcellcon = ifaces.mk_cellconn()
 155     pincon = ifaces.mk_pincon()
 156     inst = ifaces.extfastifinstance()
 157     mkplic = ifaces.mk_plic()
 158     numsloirqs = ifaces.mk_sloirqsdef()
 159     ifacedef = ifaces.mk_ext_ifacedef()
 160     dma = ifaces.mk_dma_irq()
 161     num_dmachannels = ifaces.num_dmachannels()
 162
 163     with open(soc, "w") as bsv_file:
 164         with open(soct) as f:
 165             soct = f.read()
 166         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 167                                    slavedecl, mastdecl, mkcon,
 168                                    inst, dma, num_dmachannels,
 169                                    pincon, regdef, fnaddrmap,
 170                                    ))
 171
 172     with open(fastmf, "w") as bsv_file:
 173         with open(fastmt) as f:
 174             fastmt = f.read()
 175         bsv_file.write(fastmt.format(regdef, slavedecl, mastdecl, fnaddrmap))
 176
 177
 178 def write_bus(bus, p, ifaces):
 179     # package and interface declaration followed by
 180     # the generic io_cell definition
 181     with open(bus, "w") as bsv_file:
 182         ifaces.busfmt(bsv_file)
 183
 184
 185 def write_pmp(pmp, p, ifaces, iocells):
 186     # package and interface declaration followed by
 187     # the generic io_cell definition
 188     with open(pmp, "w") as bsv_file:
 189         bsv_file.write(header)
 190
 191         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 192         bsv_file.write('''\
 193       (*always_ready,always_enabled*)
 194       interface MuxSelectionLines;
 195
 196       // declare the method which will capture the user pin-mux
 197       // selection values.The width of the input is dependent on the number
 198       // of muxes happening per IO. For now we have a generalized width
 199       // where each IO will have the same number of muxes.''')
 200
 201         for cell in p.muxed_cells:
 202             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 203
 204         bsv_file.write("\n      endinterface\n")
 205
 206         bsv_file.write('''
 207
 208       interface IOCellSide;
 209       // declare the interface to the IO cells.
 210       // Each IO cell will have 1 input field (output from pin mux)
 211       // and an output and out-enable field (input to pinmux)''')
 212
 213         # == create method definitions for all iocell interfaces ==#
 214         iocells.ifacefmt(bsv_file)
 215
 216         # ===== finish interface definition and start module definition=======
 217         bsv_file.write("\n      endinterface\n")
 218
 219         ifaces.ifacepfmt(bsv_file)
 220         # ===== io cell definition =======
 221         bsv_file.write('''
 222       (*always_ready,always_enabled*)
 223       interface PeripheralSide;
 224       // declare the interface to the peripherals
 225       // Each peripheral's function will be either an input, output
 226       // or be bi-directional.  an input field will be an output from the
 227       // peripheral and an output field will be an input to the peripheral.
 228       // Bi-directional functions also have an output-enable (which
 229       // again comes *in* from the peripheral)''')
 230         # ==============================================================
 231
 232         # == create method definitions for all peripheral interfaces ==#
 233         ifaces.ifacefmt2(bsv_file)
 234         bsv_file.write("\n      endinterface\n")
 235
 236         # ===== finish interface definition and start module definition=======
 237         bsv_file.write('''
 238
 239    interface Ifc_pinmux;
 240       // this interface controls how each IO cell is routed.  setting
 241       // any given IO cell's mux control value will result in redirection
 242       // of not just the input or output to different peripheral functions
 243       // but also the *direction* control - if appropriate - as well.
 244       interface MuxSelectionLines mux_lines;
 245
 246       // this interface contains the inputs, outputs and direction-control
 247       // lines for all peripherals.  GPIO is considered to also be just
 248       // a peripheral because it also has in, out and direction-control.
 249       interface PeripheralSide peripheral_side;
 250
 251       // this interface is to be linked to the individual IO cells.
 252       // if looking at a "non-muxed" GPIO design, basically the
 253       // IO cell input, output and direction-control wires are cut
 254       // (giving six pairs of dangling wires, named left and right)
 255       // these iocells are routed in their place on one side ("left")
 256       // and the matching *GPIO* peripheral interfaces in/out/dir
 257       // connect to the OTHER side ("right").  the result is that
 258       // the muxer settings end up controlling the routing of where
 259       // the I/O from the IOcell actually goes.
 260       interface IOCellSide iocell_side;
 261    endinterface
 262
 263    (*synthesize*)
 264    module mkpinmux(Ifc_pinmux);
 265 ''')
 266         # ====================================================================
 267
 268         # ======================= create wire and registers =================#
 269         bsv_file.write('''
 270       // the followins wires capture the pin-mux selection
 271       // values for each mux assigned to a CELL
 272 ''')
 273         for cell in p.muxed_cells:
 274             bsv_file.write(mux_interface.wirefmt(
 275                 cell[0], cell_bit_width))
 276
 277         iocells.wirefmt(bsv_file)
 278         ifaces.wirefmt(bsv_file)
 279
 280         bsv_file.write("\n")
 281         # ====================================================================
 282         # ========================= Actual pinmuxing ========================#
 283         bsv_file.write('''
 284       /*====== This where the muxing starts for each io-cell======*/
 285       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 286 ''')
 287         bsv_file.write(p.pinmux)
 288         bsv_file.write('''
 289       /*============================================================*/
 290 ''')
 291         # ====================================================================
 292         # ================= interface definitions for each method =============#
 293         bsv_file.write('''
 294     interface mux_lines = interface MuxSelectionLines
 295 ''')
 296         for cell in p.muxed_cells:
 297             bsv_file.write(
 298                 mux_interface.ifacedef(
 299                     cell[0], cell_bit_width))
 300         bsv_file.write("\n    endinterface;")
 301
 302         bsv_file.write('''
 303
 304     interface iocell_side = interface IOCellSide
 305 ''')
 306         iocells.ifacedef(bsv_file)
 307         bsv_file.write("\n     endinterface;")
 308
 309         bsv_file.write('''
 310
 311      interface peripheral_side = interface PeripheralSide
 312 ''')
 313         ifaces.ifacedef2(bsv_file)
 314         bsv_file.write("\n      endinterface;")
 315
 316         bsv_file.write(footer)
 317         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 318         # ======================================================================
 319
 320
 321 def write_ptp(ptp, p, ifaces):
 322     with open(ptp, 'w') as bsv_file:
 323         bsv_file.write(copyright + '''
 324 package PinTop;
 325     import pinmux::*;
 326     interface Ifc_PintTop;
 327         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 328         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 329         interface PeripheralSide peripheral_side;
 330     endinterface
 331
 332     module mkPinTop(Ifc_PintTop);
 333         // instantiate the pin-mux module here
 334         Ifc_pinmux pinmux <-mkpinmux;
 335
 336         // declare the registers which will be used to mux the IOs
 337 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 338
 339         cell_bit_width = str(p.cell_bitwidth)
 340         for cell in p.muxed_cells:
 341             bsv_file.write('''
 342                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 343                 cell_bit_width, cell[0]))
 344
 345         bsv_file.write('''
 346         // rule to connect the registers to the selection lines of the
 347         // pin-mux module
 348         rule connect_selection_registers;''')
 349
 350         for cell in p.muxed_cells:
 351             bsv_file.write('''
 352           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 353
 354         bsv_file.write('''
 355         endrule
 356         // method definitions for the write user interface
 357         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 358           Bool err=False;
 359           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 360                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 361         index = 0
 362         for cell in p.muxed_cells:
 363             bsv_file.write('''
 364             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 365             index = index + 1
 366
 367         bsv_file.write('''
 368             default: err=True;
 369           endcase
 370           return err;
 371         endmethod''')
 372
 373         bsv_file.write('''
 374         // method definitions for the read user interface
 375         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 376           Bool err=False;
 377           Bit#(32) data=0;
 378           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 379                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 380         index = 0
 381         for cell in p.muxed_cells:
 382             bsv_file.write('''
 383                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 384             index = index + 1
 385
 386         bsv_file.write('''
 387             default:err=True;
 388           endcase
 389           return tuple2(err,data);
 390         endmethod
 391         interface peripheral_side=pinmux.peripheral_side;
 392     endmodule
 393 endpackage
 394 ''')
 395
 396
 397 def write_bvp(bvp, p, ifaces):
 398     # ######## Generate bus transactors ################
 399     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 400               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 401     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 402         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 403
 404     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 405     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 406     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 407               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 408     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 409         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 410     with open(bvp, 'w') as bsv_file:
 411         # assume here that all muxes have a 1:1 gpio
 412         cfg = []
 413         decl = []
 414         idec = []
 415         iks = sorted(ifaces.keys())
 416         for iname in iks:
 417             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 418                 continue
 419             bank = iname[4:]
 420             ifc = ifaces[iname]
 421             npins = len(ifc.pinspecs)
 422             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 423                                       0,  # USERSPACE
 424                                       bank, npins))
 425             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 426                                      0,  # USERSPACE
 427                                      bank, npins))
 428             decl.append(gpiodec.format(npins, bank))
 429             decl.append(muxdec .format(npins, bank))
 430             idec.append(gpioifc.format(bank))
 431             idec.append(muxifc.format(bank))
 432         print dir(ifaces)
 433         print ifaces.items()
 434         print dir(ifaces['gpioa'])
 435         print ifaces['gpioa'].pinspecs
 436         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 437         gpiocfg = '\n'.join(cfg)
 438         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 439     # ##################################################
 440
 441
 442 def write_instances(idef, p, ifaces):
 443     with open(idef, 'w') as bsv_file:
 444         txt = '''\
 445 `define ADDR {0}
 446 `define PADDR {0}
 447 `define DATA {1}
 448 `define Reg_width {1}
 449 `define USERSPACE 0
 450 `define RV64
 451
 452 // TODO: work out if these are needed
 453 `define PWM_AXI4Lite
 454 `define PRFDEPTH 6
 455 `define VADDR 39
 456 `define DCACHE_BLOCK_SIZE 4
 457 `define DCACHE_WORD_SIZE 8
 458 `define PERFMONITORS                            64
 459 `define DCACHE_WAYS 4
 460 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 461
 462 // CLINT
 463     `define ClintBase       'h02000000
 464     `define ClintEnd        'h020BFFFF
 465
 466 `define PLIC
 467         `define PLICBase                'h0c000000
 468         `define PLICEnd         'h10000000
 469 `define INTERRUPT_PINS 64
 470
 471 `define BAUD_RATE 130
 472 `ifdef simulate
 473   `define BAUD_RATE 5 //130 //
 474 `endif
 475 '''
 476         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))