src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     soc = os.path.join(bp, 'soc.bsv')
  90     soct = os.path.join(cwd, 'soc_template.bsv')
  91
  92     write_pmp(pmp, p, ifaces, iocells)
  93     write_ptp(ptp, p, ifaces)
  94     write_bvp(bvp, p, ifaces)
  95     write_bus(bus, p, ifaces)
  96     write_instances(idef, p, ifaces)
  97     write_slow(slow, slowt, p, ifaces, iocells)
  98     write_soc(soc, soct, p, ifaces, iocells)
  99
 100
 101 def write_slow(slow, slowt, p, ifaces, iocells):
 102     """ write out the slow_peripherals.bsv file.
 103         joins all the peripherals together into one AXI Lite interface
 104     """
 105     with open(slowt) as bsv_file:
 106         slowt = bsv_file.read()
 107     imports = ifaces.slowimport()
 108     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 109     regdef = ifaces.axi_reg_def()
 110     slavedecl = ifaces.axi_slave_idx()
 111     fnaddrmap = ifaces.axi_addr_map()
 112     mkslow = ifaces.mkslow_peripheral()
 113     mkcon = ifaces.mk_connection()
 114     mkcellcon = ifaces.mk_cellconn()
 115     pincon = ifaces.mk_pincon()
 116     inst = ifaces.extifinstance()
 117     inst2 = ifaces.extifinstance2()
 118     mkplic = ifaces.mk_plic()
 119     numsloirqs = ifaces.mk_sloirqsdef()
 120     ifacedef = ifaces.mk_ext_ifacedef()
 121     ifacedef = ifaces.mk_ext_ifacedef()
 122     with open(slow, "w") as bsv_file:
 123         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 124                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 125                                     pincon, inst, mkplic,
 126                                     numsloirqs, ifacedef,
 127                                     inst2))
 128
 129
 130 def write_soc(soc, soct, p, ifaces, iocells):
 131     """ write out the soc.bsv file.
 132         joins all the peripherals together as AXI Masters
 133     """
 134     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 135     with open(soct) as bsv_file:
 136         soct = bsv_file.read()
 137     imports = ifaces.slowimport()
 138     ifdecl = ifaces.fastifdecl()
 139 #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 140     regdef = ifaces.axi_reg_def()
 141     slavedecl = ifaces.axi_fastslave_idx()
 142     mastdecl = ifaces.axi_master_idx()
 143     fnaddrmap = ifaces.axi_addr_map()
 144     mkfast = ifaces.mkfast_peripheral()
 145     mkcon = ifaces.mk_fast_connection()
 146     mkcellcon = ifaces.mk_cellconn()
 147     pincon = ifaces.mk_pincon()
 148     inst = ifaces.extfastifinstance()
 149     mkplic = ifaces.mk_plic()
 150     numsloirqs = ifaces.mk_sloirqsdef()
 151     ifacedef = ifaces.mk_ext_ifacedef()
 152     dma = ifaces.mk_dma_irq()
 153     num_dmachannels = ifaces.num_dmachannels()
 154     with open(soc, "w") as bsv_file:
 155         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 156                                    slavedecl, mastdecl, mkcon,
 157                                    inst, dma, num_dmachannels,
 158                                    pincon,
 159                                    ))
 160
 161
 162 def write_bus(bus, p, ifaces):
 163     # package and interface declaration followed by
 164     # the generic io_cell definition
 165     with open(bus, "w") as bsv_file:
 166         ifaces.busfmt(bsv_file)
 167
 168
 169 def write_pmp(pmp, p, ifaces, iocells):
 170     # package and interface declaration followed by
 171     # the generic io_cell definition
 172     with open(pmp, "w") as bsv_file:
 173         bsv_file.write(header)
 174
 175         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 176         bsv_file.write('''\
 177       (*always_ready,always_enabled*)
 178       interface MuxSelectionLines;
 179
 180       // declare the method which will capture the user pin-mux
 181       // selection values.The width of the input is dependent on the number
 182       // of muxes happening per IO. For now we have a generalized width
 183       // where each IO will have the same number of muxes.''')
 184
 185         for cell in p.muxed_cells:
 186             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 187
 188         bsv_file.write("\n      endinterface\n")
 189
 190         bsv_file.write('''
 191
 192       interface IOCellSide;
 193       // declare the interface to the IO cells.
 194       // Each IO cell will have 1 input field (output from pin mux)
 195       // and an output and out-enable field (input to pinmux)''')
 196
 197         # == create method definitions for all iocell interfaces ==#
 198         iocells.ifacefmt(bsv_file)
 199
 200         # ===== finish interface definition and start module definition=======
 201         bsv_file.write("\n      endinterface\n")
 202
 203         ifaces.ifacepfmt(bsv_file)
 204         # ===== io cell definition =======
 205         bsv_file.write('''
 206       (*always_ready,always_enabled*)
 207       interface PeripheralSide;
 208       // declare the interface to the peripherals
 209       // Each peripheral's function will be either an input, output
 210       // or be bi-directional.  an input field will be an output from the
 211       // peripheral and an output field will be an input to the peripheral.
 212       // Bi-directional functions also have an output-enable (which
 213       // again comes *in* from the peripheral)''')
 214         # ==============================================================
 215
 216         # == create method definitions for all peripheral interfaces ==#
 217         ifaces.ifacefmt2(bsv_file)
 218         bsv_file.write("\n      endinterface\n")
 219
 220         # ===== finish interface definition and start module definition=======
 221         bsv_file.write('''
 222
 223    interface Ifc_pinmux;
 224       // this interface controls how each IO cell is routed.  setting
 225       // any given IO cell's mux control value will result in redirection
 226       // of not just the input or output to different peripheral functions
 227       // but also the *direction* control - if appropriate - as well.
 228       interface MuxSelectionLines mux_lines;
 229
 230       // this interface contains the inputs, outputs and direction-control
 231       // lines for all peripherals.  GPIO is considered to also be just
 232       // a peripheral because it also has in, out and direction-control.
 233       interface PeripheralSide peripheral_side;
 234
 235       // this interface is to be linked to the individual IO cells.
 236       // if looking at a "non-muxed" GPIO design, basically the
 237       // IO cell input, output and direction-control wires are cut
 238       // (giving six pairs of dangling wires, named left and right)
 239       // these iocells are routed in their place on one side ("left")
 240       // and the matching *GPIO* peripheral interfaces in/out/dir
 241       // connect to the OTHER side ("right").  the result is that
 242       // the muxer settings end up controlling the routing of where
 243       // the I/O from the IOcell actually goes.
 244       interface IOCellSide iocell_side;
 245    endinterface
 246
 247    (*synthesize*)
 248    module mkpinmux(Ifc_pinmux);
 249 ''')
 250         # ====================================================================
 251
 252         # ======================= create wire and registers =================#
 253         bsv_file.write('''
 254       // the followins wires capture the pin-mux selection
 255       // values for each mux assigned to a CELL
 256 ''')
 257         for cell in p.muxed_cells:
 258             bsv_file.write(mux_interface.wirefmt(
 259                 cell[0], cell_bit_width))
 260
 261         iocells.wirefmt(bsv_file)
 262         ifaces.wirefmt(bsv_file)
 263
 264         bsv_file.write("\n")
 265         # ====================================================================
 266         # ========================= Actual pinmuxing ========================#
 267         bsv_file.write('''
 268       /*====== This where the muxing starts for each io-cell======*/
 269       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 270 ''')
 271         bsv_file.write(p.pinmux)
 272         bsv_file.write('''
 273       /*============================================================*/
 274 ''')
 275         # ====================================================================
 276         # ================= interface definitions for each method =============#
 277         bsv_file.write('''
 278     interface mux_lines = interface MuxSelectionLines
 279 ''')
 280         for cell in p.muxed_cells:
 281             bsv_file.write(
 282                 mux_interface.ifacedef(
 283                     cell[0], cell_bit_width))
 284         bsv_file.write("\n    endinterface;")
 285
 286         bsv_file.write('''
 287
 288     interface iocell_side = interface IOCellSide
 289 ''')
 290         iocells.ifacedef(bsv_file)
 291         bsv_file.write("\n     endinterface;")
 292
 293         bsv_file.write('''
 294
 295      interface peripheral_side = interface PeripheralSide
 296 ''')
 297         ifaces.ifacedef2(bsv_file)
 298         bsv_file.write("\n      endinterface;")
 299
 300         bsv_file.write(footer)
 301         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 302         # ======================================================================
 303
 304
 305 def write_ptp(ptp, p, ifaces):
 306     with open(ptp, 'w') as bsv_file:
 307         bsv_file.write(copyright + '''
 308 package PinTop;
 309     import pinmux::*;
 310     interface Ifc_PintTop;
 311         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 312         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 313         interface PeripheralSide peripheral_side;
 314     endinterface
 315
 316     module mkPinTop(Ifc_PintTop);
 317         // instantiate the pin-mux module here
 318         Ifc_pinmux pinmux <-mkpinmux;
 319
 320         // declare the registers which will be used to mux the IOs
 321 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 322
 323         cell_bit_width = str(p.cell_bitwidth)
 324         for cell in p.muxed_cells:
 325             bsv_file.write('''
 326                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 327                 cell_bit_width, cell[0]))
 328
 329         bsv_file.write('''
 330         // rule to connect the registers to the selection lines of the
 331         // pin-mux module
 332         rule connect_selection_registers;''')
 333
 334         for cell in p.muxed_cells:
 335             bsv_file.write('''
 336           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 337
 338         bsv_file.write('''
 339         endrule
 340         // method definitions for the write user interface
 341         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 342           Bool err=False;
 343           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 344                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 345         index = 0
 346         for cell in p.muxed_cells:
 347             bsv_file.write('''
 348             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 349             index = index + 1
 350
 351         bsv_file.write('''
 352             default: err=True;
 353           endcase
 354           return err;
 355         endmethod''')
 356
 357         bsv_file.write('''
 358         // method definitions for the read user interface
 359         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 360           Bool err=False;
 361           Bit#(32) data=0;
 362           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 363                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 364         index = 0
 365         for cell in p.muxed_cells:
 366             bsv_file.write('''
 367                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 368             index = index + 1
 369
 370         bsv_file.write('''
 371             default:err=True;
 372           endcase
 373           return tuple2(err,data);
 374         endmethod
 375         interface peripheral_side=pinmux.peripheral_side;
 376     endmodule
 377 endpackage
 378 ''')
 379
 380
 381 def write_bvp(bvp, p, ifaces):
 382     # ######## Generate bus transactors ################
 383     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 384               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 385     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 386         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 387
 388     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 389     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 390     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 391               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 392     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 393         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 394     with open(bvp, 'w') as bsv_file:
 395         # assume here that all muxes have a 1:1 gpio
 396         cfg = []
 397         decl = []
 398         idec = []
 399         iks = sorted(ifaces.keys())
 400         for iname in iks:
 401             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 402                 continue
 403             bank = iname[4:]
 404             ifc = ifaces[iname]
 405             npins = len(ifc.pinspecs)
 406             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 407                                       0,  # USERSPACE
 408                                       bank, npins))
 409             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 410                                      0,  # USERSPACE
 411                                      bank, npins))
 412             decl.append(gpiodec.format(npins, bank))
 413             decl.append(muxdec .format(npins, bank))
 414             idec.append(gpioifc.format(bank))
 415             idec.append(muxifc.format(bank))
 416         print dir(ifaces)
 417         print ifaces.items()
 418         print dir(ifaces['gpioa'])
 419         print ifaces['gpioa'].pinspecs
 420         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 421         gpiocfg = '\n'.join(cfg)
 422         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 423     # ##################################################
 424
 425
 426 def write_instances(idef, p, ifaces):
 427     with open(idef, 'w') as bsv_file:
 428         txt = '''\
 429 `define ADDR {0}
 430 `define PADDR {0}
 431 `define DATA {1}
 432 `define Reg_width {1}
 433 `define USERSPACE 0
 434
 435 // TODO: work out if these are needed
 436 `define PWM_AXI4Lite
 437 `define PRFDEPTH 6
 438 `define VADDR 39
 439 `define DCACHE_BLOCK_SIZE 4
 440 `define DCACHE_WORD_SIZE 8
 441 `define PERFMONITORS                            64
 442 `define DCACHE_WAYS 4
 443 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 444 `define PLIC
 445         `define PLICBase                'h0c000000
 446         `define PLICEnd         'h10000000
 447 `define INTERRUPT_PINS 64
 448
 449 `define BAUD_RATE 130
 450 `ifdef simulate
 451   `define BAUD_RATE 5 //130 //
 452 `endif
 453 '''
 454         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))