src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     soc = os.path.join(bp, 'soc.bsv')
  90     soct = os.path.join(cwd, 'soc_template.bsv')
  91
  92     write_pmp(pmp, p, ifaces, iocells)
  93     write_ptp(ptp, p, ifaces)
  94     write_bvp(bvp, p, ifaces)
  95     write_bus(bus, p, ifaces)
  96     write_instances(idef, p, ifaces)
  97     write_slow(slow, slowt, p, ifaces, iocells)
  98     write_soc(soc, soct, p, ifaces, iocells)
  99
 100
 101 def write_slow(slow, slowt, p, ifaces, iocells):
 102     """ write out the slow_peripherals.bsv file.
 103         joins all the peripherals together into one AXI Lite interface
 104     """
 105     with open(slowt) as bsv_file:
 106         slowt = bsv_file.read()
 107     imports = ifaces.slowimport()
 108     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 109     regdef = ifaces.axi_reg_def()
 110     slavedecl = ifaces.axi_slave_idx()
 111     fnaddrmap = ifaces.axi_addr_map()
 112     mkslow = ifaces.mkslow_peripheral()
 113     mkcon = ifaces.mk_connection()
 114     mkcellcon = ifaces.mk_cellconn()
 115     pincon = ifaces.mk_pincon()
 116     inst = ifaces.extifinstance()
 117     inst2 = ifaces.extifinstance2()
 118     mkplic = ifaces.mk_plic()
 119     numsloirqs = ifaces.mk_sloirqsdef()
 120     ifacedef = ifaces.mk_ext_ifacedef()
 121     ifacedef = ifaces.mk_ext_ifacedef()
 122     with open(slow, "w") as bsv_file:
 123         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 124                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 125                                     pincon, inst, mkplic,
 126                                     numsloirqs, ifacedef,
 127                                     inst2))
 128
 129 def write_soc(soc, soct, p, ifaces, iocells):
 130     """ write out the soc.bsv file.
 131         joins all the peripherals together as AXI Masters
 132     """
 133     ifaces.fastbusmode = True # side-effects... shouldn't really do this
 134     with open(soct) as bsv_file:
 135         soct = bsv_file.read()
 136     imports = ifaces.slowimport()
 137     ifdecl = ifaces.fastifdecl()
 138 #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 139     regdef = ifaces.axi_reg_def()
 140     slavedecl = ifaces.axi_fastslave_idx()
 141     mastdecl = ifaces.axi_master_idx()
 142     fnaddrmap = ifaces.axi_addr_map()
 143     mkfast = ifaces.mkfast_peripheral()
 144     mkcon = ifaces.mk_fast_connection()
 145     mkcellcon = ifaces.mk_cellconn()
 146     pincon = ifaces.mk_pincon()
 147     inst = ifaces.extfastifinstance()
 148     mkplic = ifaces.mk_plic()
 149     numsloirqs = ifaces.mk_sloirqsdef()
 150     ifacedef = ifaces.mk_ext_ifacedef()
 151     dma = ifaces.mk_dma_irq()
 152     num_dmachannels = ifaces.num_dmachannels()
 153     with open(soc, "w") as bsv_file:
 154         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 155                             slavedecl, mastdecl, mkcon,
 156                             inst, dma, num_dmachannels,
 157                             #'', '' #regdef, slavedecl,
 158                             #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
 159                             #pincon, inst, mkplic,
 160                             #numsloirqs, ifacedef))
 161                                   ))
 162
 163
 164 def write_bus(bus, p, ifaces):
 165     # package and interface declaration followed by
 166     # the generic io_cell definition
 167     with open(bus, "w") as bsv_file:
 168         ifaces.busfmt(bsv_file)
 169
 170
 171 def write_pmp(pmp, p, ifaces, iocells):
 172     # package and interface declaration followed by
 173     # the generic io_cell definition
 174     with open(pmp, "w") as bsv_file:
 175         bsv_file.write(header)
 176
 177         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 178         bsv_file.write('''\
 179       (*always_ready,always_enabled*)
 180       interface MuxSelectionLines;
 181
 182       // declare the method which will capture the user pin-mux
 183       // selection values.The width of the input is dependent on the number
 184       // of muxes happening per IO. For now we have a generalized width
 185       // where each IO will have the same number of muxes.''')
 186
 187         for cell in p.muxed_cells:
 188             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 189
 190         bsv_file.write("\n      endinterface\n")
 191
 192         bsv_file.write('''
 193
 194       interface IOCellSide;
 195       // declare the interface to the IO cells.
 196       // Each IO cell will have 1 input field (output from pin mux)
 197       // and an output and out-enable field (input to pinmux)''')
 198
 199         # == create method definitions for all iocell interfaces ==#
 200         iocells.ifacefmt(bsv_file)
 201
 202         # ===== finish interface definition and start module definition=======
 203         bsv_file.write("\n      endinterface\n")
 204
 205         ifaces.ifacepfmt(bsv_file)
 206         # ===== io cell definition =======
 207         bsv_file.write('''
 208       (*always_ready,always_enabled*)
 209       interface PeripheralSide;
 210       // declare the interface to the peripherals
 211       // Each peripheral's function will be either an input, output
 212       // or be bi-directional.  an input field will be an output from the
 213       // peripheral and an output field will be an input to the peripheral.
 214       // Bi-directional functions also have an output-enable (which
 215       // again comes *in* from the peripheral)''')
 216         # ==============================================================
 217
 218         # == create method definitions for all peripheral interfaces ==#
 219         ifaces.ifacefmt2(bsv_file)
 220         bsv_file.write("\n      endinterface\n")
 221
 222         # ===== finish interface definition and start module definition=======
 223         bsv_file.write('''
 224
 225    interface Ifc_pinmux;
 226       // this interface controls how each IO cell is routed.  setting
 227       // any given IO cell's mux control value will result in redirection
 228       // of not just the input or output to different peripheral functions
 229       // but also the *direction* control - if appropriate - as well.
 230       interface MuxSelectionLines mux_lines;
 231
 232       // this interface contains the inputs, outputs and direction-control
 233       // lines for all peripherals.  GPIO is considered to also be just
 234       // a peripheral because it also has in, out and direction-control.
 235       interface PeripheralSide peripheral_side;
 236
 237       // this interface is to be linked to the individual IO cells.
 238       // if looking at a "non-muxed" GPIO design, basically the
 239       // IO cell input, output and direction-control wires are cut
 240       // (giving six pairs of dangling wires, named left and right)
 241       // these iocells are routed in their place on one side ("left")
 242       // and the matching *GPIO* peripheral interfaces in/out/dir
 243       // connect to the OTHER side ("right").  the result is that
 244       // the muxer settings end up controlling the routing of where
 245       // the I/O from the IOcell actually goes.
 246       interface IOCellSide iocell_side;
 247    endinterface
 248
 249    (*synthesize*)
 250    module mkpinmux(Ifc_pinmux);
 251 ''')
 252         # ====================================================================
 253
 254         # ======================= create wire and registers =================#
 255         bsv_file.write('''
 256       // the followins wires capture the pin-mux selection
 257       // values for each mux assigned to a CELL
 258 ''')
 259         for cell in p.muxed_cells:
 260             bsv_file.write(mux_interface.wirefmt(
 261                 cell[0], cell_bit_width))
 262
 263         iocells.wirefmt(bsv_file)
 264         ifaces.wirefmt(bsv_file)
 265
 266         bsv_file.write("\n")
 267         # ====================================================================
 268         # ========================= Actual pinmuxing ========================#
 269         bsv_file.write('''
 270       /*====== This where the muxing starts for each io-cell======*/
 271       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 272 ''')
 273         bsv_file.write(p.pinmux)
 274         bsv_file.write('''
 275       /*============================================================*/
 276 ''')
 277         # ====================================================================
 278         # ================= interface definitions for each method =============#
 279         bsv_file.write('''
 280     interface mux_lines = interface MuxSelectionLines
 281 ''')
 282         for cell in p.muxed_cells:
 283             bsv_file.write(
 284                 mux_interface.ifacedef(
 285                     cell[0], cell_bit_width))
 286         bsv_file.write("\n    endinterface;")
 287
 288         bsv_file.write('''
 289
 290     interface iocell_side = interface IOCellSide
 291 ''')
 292         iocells.ifacedef(bsv_file)
 293         bsv_file.write("\n     endinterface;")
 294
 295         bsv_file.write('''
 296
 297      interface peripheral_side = interface PeripheralSide
 298 ''')
 299         ifaces.ifacedef2(bsv_file)
 300         bsv_file.write("\n      endinterface;")
 301
 302         bsv_file.write(footer)
 303         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 304         # ======================================================================
 305
 306
 307 def write_ptp(ptp, p, ifaces):
 308     with open(ptp, 'w') as bsv_file:
 309         bsv_file.write(copyright + '''
 310 package PinTop;
 311     import pinmux::*;
 312     interface Ifc_PintTop;
 313         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 314         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 315         interface PeripheralSide peripheral_side;
 316     endinterface
 317
 318     module mkPinTop(Ifc_PintTop);
 319         // instantiate the pin-mux module here
 320         Ifc_pinmux pinmux <-mkpinmux;
 321
 322         // declare the registers which will be used to mux the IOs
 323 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 324
 325         cell_bit_width = str(p.cell_bitwidth)
 326         for cell in p.muxed_cells:
 327             bsv_file.write('''
 328                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 329                 cell_bit_width, cell[0]))
 330
 331         bsv_file.write('''
 332         // rule to connect the registers to the selection lines of the
 333         // pin-mux module
 334         rule connect_selection_registers;''')
 335
 336         for cell in p.muxed_cells:
 337             bsv_file.write('''
 338           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 339
 340         bsv_file.write('''
 341         endrule
 342         // method definitions for the write user interface
 343         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 344           Bool err=False;
 345           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 346                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 347         index = 0
 348         for cell in p.muxed_cells:
 349             bsv_file.write('''
 350             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 351             index = index + 1
 352
 353         bsv_file.write('''
 354             default: err=True;
 355           endcase
 356           return err;
 357         endmethod''')
 358
 359         bsv_file.write('''
 360         // method definitions for the read user interface
 361         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 362           Bool err=False;
 363           Bit#(32) data=0;
 364           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 365                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 366         index = 0
 367         for cell in p.muxed_cells:
 368             bsv_file.write('''
 369                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 370             index = index + 1
 371
 372         bsv_file.write('''
 373             default:err=True;
 374           endcase
 375           return tuple2(err,data);
 376         endmethod
 377         interface peripheral_side=pinmux.peripheral_side;
 378     endmodule
 379 endpackage
 380 ''')
 381
 382
 383 def write_bvp(bvp, p, ifaces):
 384     # ######## Generate bus transactors ################
 385     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 386               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 387     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 388         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 389
 390     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 391     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 392     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 393               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 394     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 395         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 396     with open(bvp, 'w') as bsv_file:
 397         # assume here that all muxes have a 1:1 gpio
 398         cfg = []
 399         decl = []
 400         idec = []
 401         iks = sorted(ifaces.keys())
 402         for iname in iks:
 403             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 404                 continue
 405             bank = iname[4:]
 406             ifc = ifaces[iname]
 407             npins = len(ifc.pinspecs)
 408             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 409                                       0,  # USERSPACE
 410                                       bank, npins))
 411             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 412                                      0,  # USERSPACE
 413                                      bank, npins))
 414             decl.append(gpiodec.format(npins, bank))
 415             decl.append(muxdec .format(npins, bank))
 416             idec.append(gpioifc.format(bank))
 417             idec.append(muxifc.format(bank))
 418         print dir(ifaces)
 419         print ifaces.items()
 420         print dir(ifaces['gpioa'])
 421         print ifaces['gpioa'].pinspecs
 422         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 423         gpiocfg = '\n'.join(cfg)
 424         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 425     # ##################################################
 426
 427
 428 def write_instances(idef, p, ifaces):
 429     with open(idef, 'w') as bsv_file:
 430         txt = '''\
 431 `define ADDR {0}
 432 `define PADDR {0}
 433 `define DATA {1}
 434 `define Reg_width {1}
 435 `define USERSPACE 0
 436
 437 // TODO: work out if these are needed
 438 `define PWM_AXI4Lite
 439 `define PRFDEPTH 6
 440 `define VADDR 39
 441 `define DCACHE_BLOCK_SIZE 4
 442 `define DCACHE_WORD_SIZE 8
 443 `define PERFMONITORS                            64
 444 `define DCACHE_WAYS 4
 445 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 446 `define PLIC
 447         `define PLICBase                'h0c000000
 448         `define PLICEnd         'h10000000
 449 `define INTERRUPT_PINS 64
 450
 451 `define BAUD_RATE 130
 452 `ifdef simulate
 453   `define BAUD_RATE 5 //130 //
 454 `endif
 455 '''
 456         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))