src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     soc = os.path.join(bp, 'soc.bsv')
  90     soct = os.path.join(cwd, 'soc_template.bsv')
  91
  92     write_pmp(pmp, p, ifaces, iocells)
  93     write_ptp(ptp, p, ifaces)
  94     write_bvp(bvp, p, ifaces)
  95     write_bus(bus, p, ifaces)
  96     write_instances(idef, p, ifaces)
  97     write_slow(slow, slowt, p, ifaces, iocells)
  98     write_soc(soc, soct, p, ifaces, iocells)
  99
 100
 101 def write_slow(slow, slowt, p, ifaces, iocells):
 102     """ write out the slow_peripherals.bsv file.
 103         joins all the peripherals together into one AXI Lite interface
 104     """
 105     with open(slowt) as bsv_file:
 106         slowt = bsv_file.read()
 107     imports = ifaces.slowimport()
 108     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 109     regdef = ifaces.axi_reg_def()
 110     slavedecl = ifaces.axi_slave_idx()
 111     fnaddrmap = ifaces.axi_addr_map()
 112     mkslow = ifaces.mkslow_peripheral()
 113     mkcon = ifaces.mk_connection()
 114     mkcellcon = ifaces.mk_cellconn()
 115     pincon = ifaces.mk_pincon()
 116     inst = ifaces.extifinstance()
 117     mkplic = ifaces.mk_plic()
 118     numsloirqs = ifaces.mk_sloirqsdef()
 119     ifacedef = ifaces.mk_ext_ifacedef()
 120     ifacedef = ifaces.mk_ext_ifacedef()
 121     with open(slow, "w") as bsv_file:
 122         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 123                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 124                                     pincon, inst, mkplic,
 125                                     numsloirqs, ifacedef))
 126
 127 def write_soc(soc, soct, p, ifaces, iocells):
 128     """ write out the soc.bsv file.
 129         joins all the peripherals together as AXI Masters
 130     """
 131     ifaces.fastbusmode = True # side-effects... shouldn't really do this
 132     with open(soct) as bsv_file:
 133         soct = bsv_file.read()
 134     imports = ifaces.slowimport()
 135     ifdecl = "" #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 136     regdef = ifaces.axi_reg_def()
 137     slavedecl = ifaces.axi_fastslave_idx()
 138     mastdecl = ifaces.axi_master_idx()
 139     fnaddrmap = ifaces.axi_addr_map()
 140     mkfast = ifaces.mkfast_peripheral()
 141     mkcon = ifaces.mk_fast_connection()
 142     mkcellcon = ifaces.mk_cellconn()
 143     pincon = ifaces.mk_pincon()
 144     inst = ifaces.extifinstance()
 145     mkplic = ifaces.mk_plic()
 146     numsloirqs = ifaces.mk_sloirqsdef()
 147     ifacedef = ifaces.mk_ext_ifacedef()
 148     ifacedef = ifaces.mk_ext_ifacedef()
 149     with open(soc, "w") as bsv_file:
 150         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 151                             slavedecl, mastdecl, mkcon,
 152                             #'', '' #regdef, slavedecl,
 153                             #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
 154                             #pincon, inst, mkplic,
 155                             #numsloirqs, ifacedef))
 156                                   ))
 157
 158
 159 def write_bus(bus, p, ifaces):
 160     # package and interface declaration followed by
 161     # the generic io_cell definition
 162     with open(bus, "w") as bsv_file:
 163         ifaces.busfmt(bsv_file)
 164
 165
 166 def write_pmp(pmp, p, ifaces, iocells):
 167     # package and interface declaration followed by
 168     # the generic io_cell definition
 169     with open(pmp, "w") as bsv_file:
 170         bsv_file.write(header)
 171
 172         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 173         bsv_file.write('''\
 174       (*always_ready,always_enabled*)
 175       interface MuxSelectionLines;
 176
 177       // declare the method which will capture the user pin-mux
 178       // selection values.The width of the input is dependent on the number
 179       // of muxes happening per IO. For now we have a generalized width
 180       // where each IO will have the same number of muxes.''')
 181
 182         for cell in p.muxed_cells:
 183             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 184
 185         bsv_file.write("\n      endinterface\n")
 186
 187         bsv_file.write('''
 188
 189       interface IOCellSide;
 190       // declare the interface to the IO cells.
 191       // Each IO cell will have 1 input field (output from pin mux)
 192       // and an output and out-enable field (input to pinmux)''')
 193
 194         # == create method definitions for all iocell interfaces ==#
 195         iocells.ifacefmt(bsv_file)
 196
 197         # ===== finish interface definition and start module definition=======
 198         bsv_file.write("\n      endinterface\n")
 199
 200         ifaces.ifacepfmt(bsv_file)
 201         # ===== io cell definition =======
 202         bsv_file.write('''
 203       (*always_ready,always_enabled*)
 204       interface PeripheralSide;
 205       // declare the interface to the peripherals
 206       // Each peripheral's function will be either an input, output
 207       // or be bi-directional.  an input field will be an output from the
 208       // peripheral and an output field will be an input to the peripheral.
 209       // Bi-directional functions also have an output-enable (which
 210       // again comes *in* from the peripheral)''')
 211         # ==============================================================
 212
 213         # == create method definitions for all peripheral interfaces ==#
 214         ifaces.ifacefmt2(bsv_file)
 215         bsv_file.write("\n      endinterface\n")
 216
 217         # ===== finish interface definition and start module definition=======
 218         bsv_file.write('''
 219
 220    interface Ifc_pinmux;
 221       // this interface controls how each IO cell is routed.  setting
 222       // any given IO cell's mux control value will result in redirection
 223       // of not just the input or output to different peripheral functions
 224       // but also the *direction* control - if appropriate - as well.
 225       interface MuxSelectionLines mux_lines;
 226
 227       // this interface contains the inputs, outputs and direction-control
 228       // lines for all peripherals.  GPIO is considered to also be just
 229       // a peripheral because it also has in, out and direction-control.
 230       interface PeripheralSide peripheral_side;
 231
 232       // this interface is to be linked to the individual IO cells.
 233       // if looking at a "non-muxed" GPIO design, basically the
 234       // IO cell input, output and direction-control wires are cut
 235       // (giving six pairs of dangling wires, named left and right)
 236       // these iocells are routed in their place on one side ("left")
 237       // and the matching *GPIO* peripheral interfaces in/out/dir
 238       // connect to the OTHER side ("right").  the result is that
 239       // the muxer settings end up controlling the routing of where
 240       // the I/O from the IOcell actually goes.
 241       interface IOCellSide iocell_side;
 242    endinterface
 243
 244    (*synthesize*)
 245    module mkpinmux(Ifc_pinmux);
 246 ''')
 247         # ====================================================================
 248
 249         # ======================= create wire and registers =================#
 250         bsv_file.write('''
 251       // the followins wires capture the pin-mux selection
 252       // values for each mux assigned to a CELL
 253 ''')
 254         for cell in p.muxed_cells:
 255             bsv_file.write(mux_interface.wirefmt(
 256                 cell[0], cell_bit_width))
 257
 258         iocells.wirefmt(bsv_file)
 259         ifaces.wirefmt(bsv_file)
 260
 261         bsv_file.write("\n")
 262         # ====================================================================
 263         # ========================= Actual pinmuxing ========================#
 264         bsv_file.write('''
 265       /*====== This where the muxing starts for each io-cell======*/
 266       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 267 ''')
 268         bsv_file.write(p.pinmux)
 269         bsv_file.write('''
 270       /*============================================================*/
 271 ''')
 272         # ====================================================================
 273         # ================= interface definitions for each method =============#
 274         bsv_file.write('''
 275     interface mux_lines = interface MuxSelectionLines
 276 ''')
 277         for cell in p.muxed_cells:
 278             bsv_file.write(
 279                 mux_interface.ifacedef(
 280                     cell[0], cell_bit_width))
 281         bsv_file.write("\n    endinterface;")
 282
 283         bsv_file.write('''
 284
 285     interface iocell_side = interface IOCellSide
 286 ''')
 287         iocells.ifacedef(bsv_file)
 288         bsv_file.write("\n     endinterface;")
 289
 290         bsv_file.write('''
 291
 292      interface peripheral_side = interface PeripheralSide
 293 ''')
 294         ifaces.ifacedef2(bsv_file)
 295         bsv_file.write("\n      endinterface;")
 296
 297         bsv_file.write(footer)
 298         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 299         # ======================================================================
 300
 301
 302 def write_ptp(ptp, p, ifaces):
 303     with open(ptp, 'w') as bsv_file:
 304         bsv_file.write(copyright + '''
 305 package PinTop;
 306     import pinmux::*;
 307     interface Ifc_PintTop;
 308         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 309         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 310         interface PeripheralSide peripheral_side;
 311     endinterface
 312
 313     module mkPinTop(Ifc_PintTop);
 314         // instantiate the pin-mux module here
 315         Ifc_pinmux pinmux <-mkpinmux;
 316
 317         // declare the registers which will be used to mux the IOs
 318 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 319
 320         cell_bit_width = str(p.cell_bitwidth)
 321         for cell in p.muxed_cells:
 322             bsv_file.write('''
 323                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 324                 cell_bit_width, cell[0]))
 325
 326         bsv_file.write('''
 327         // rule to connect the registers to the selection lines of the
 328         // pin-mux module
 329         rule connect_selection_registers;''')
 330
 331         for cell in p.muxed_cells:
 332             bsv_file.write('''
 333           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 334
 335         bsv_file.write('''
 336         endrule
 337         // method definitions for the write user interface
 338         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 339           Bool err=False;
 340           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 341                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 342         index = 0
 343         for cell in p.muxed_cells:
 344             bsv_file.write('''
 345             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 346             index = index + 1
 347
 348         bsv_file.write('''
 349             default: err=True;
 350           endcase
 351           return err;
 352         endmethod''')
 353
 354         bsv_file.write('''
 355         // method definitions for the read user interface
 356         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 357           Bool err=False;
 358           Bit#(32) data=0;
 359           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 360                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 361         index = 0
 362         for cell in p.muxed_cells:
 363             bsv_file.write('''
 364                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 365             index = index + 1
 366
 367         bsv_file.write('''
 368             default:err=True;
 369           endcase
 370           return tuple2(err,data);
 371         endmethod
 372         interface peripheral_side=pinmux.peripheral_side;
 373     endmodule
 374 endpackage
 375 ''')
 376
 377
 378 def write_bvp(bvp, p, ifaces):
 379     # ######## Generate bus transactors ################
 380     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 381               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 382     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 383         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 384
 385     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 386     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 387     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 388               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 389     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 390         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 391     with open(bvp, 'w') as bsv_file:
 392         # assume here that all muxes have a 1:1 gpio
 393         cfg = []
 394         decl = []
 395         idec = []
 396         iks = sorted(ifaces.keys())
 397         for iname in iks:
 398             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 399                 continue
 400             bank = iname[4:]
 401             ifc = ifaces[iname]
 402             npins = len(ifc.pinspecs)
 403             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 404                                       0,  # USERSPACE
 405                                       bank, npins))
 406             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 407                                      0,  # USERSPACE
 408                                      bank, npins))
 409             decl.append(gpiodec.format(npins, bank))
 410             decl.append(muxdec .format(npins, bank))
 411             idec.append(gpioifc.format(bank))
 412             idec.append(muxifc.format(bank))
 413         print dir(ifaces)
 414         print ifaces.items()
 415         print dir(ifaces['gpioa'])
 416         print ifaces['gpioa'].pinspecs
 417         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 418         gpiocfg = '\n'.join(cfg)
 419         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 420     # ##################################################
 421
 422
 423 def write_instances(idef, p, ifaces):
 424     with open(idef, 'w') as bsv_file:
 425         txt = '''\
 426 `define ADDR {0}
 427 `define PADDR {0}
 428 `define DATA {1}
 429 `define Reg_width {1}
 430 `define USERSPACE 0
 431
 432 // TODO: work out if these are needed
 433 `define PWM_AXI4Lite
 434 `define PRFDEPTH 6
 435 `define VADDR 39
 436 `define DCACHE_BLOCK_SIZE 4
 437 `define DCACHE_WORD_SIZE 8
 438 `define PERFMONITORS                            64
 439 `define DCACHE_WAYS 4
 440 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 441 `define PLIC
 442         `define PLICBase                'h0c000000
 443         `define PLICEnd         'h10000000
 444 `define INTERRUPT_PINS 64
 445
 446 `define BAUD_RATE 130
 447 `ifdef simulate
 448   `define BAUD_RATE 5 //130 //
 449 `endif
 450 '''
 451         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))