src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 '''
  43 footer = '''
  44    endmodule
  45 endpackage
  46 '''
  47
  48
  49 def pinmuxgen(pth=None, verify=True):
  50     """ populating the file with the code
  51     """
  52
  53     p = Parse(pth, verify)
  54     iocells = Interfaces()
  55     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  56     ifaces = Interfaces(pth)
  57     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  58     init(p, ifaces)
  59
  60     bp = 'bsv_src'
  61     if pth:
  62         bp = os.path.join(pth, bp)
  63     if not os.path.exists(bp):
  64         os.makedirs(bp)
  65     bl = os.path.join(bp, 'bsv_lib')
  66     if not os.path.exists(bl):
  67         os.makedirs(bl)
  68
  69     cwd = os.path.split(__file__)[0]
  70
  71     # copy over template and library files
  72     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  73                     os.path.join(bp, 'Makefile'))
  74     cwd = os.path.join(cwd, 'bsv_lib')
  75     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
  76                   'gpio.bsv', 'mux.bsv',
  77                   'AXI4_Types.bsv', 'defined_types.bsv',
  78                   'AXI4_Fabric.bsv', 'Uart16550.bsv',
  79                   'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
  80                   'Uart_bs.bsv', 'RS232_modified.bsv',
  81                   'AXI4Lite_AXI4_Bridge.bsv',
  82                   'I2C_top.bsv', 'I2C_Defs.bsv',
  83                   'plic.bsv', 'Cur_Cycle.bsv',
  84                   'ClockDiv.bsv', 'axi_addr_generator.bsv',
  85                   'jtagdtm_new.bsv', 'jtagdefines.bsv',
  86                   'sdcard_dummy.bsv',
  87                   'pwm.bsv', 'qspi.bsv', 'qspi.defs',
  88                   ]:
  89         shutil.copyfile(os.path.join(cwd, fname),
  90                         os.path.join(bl, fname))
  91
  92     bus = os.path.join(bp, 'busenable.bsv')
  93     pmp = os.path.join(bp, 'pinmux.bsv')
  94     ptp = os.path.join(bp, 'PinTop.bsv')
  95     bvp = os.path.join(bp, 'bus.bsv')
  96     idef = os.path.join(bp, 'instance_defines.bsv')
  97     slow = os.path.join(bp, 'slow_peripherals.bsv')
  98     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  99
 100     write_pmp(pmp, p, ifaces, iocells)
 101     write_ptp(ptp, p, ifaces)
 102     write_bvp(bvp, p, ifaces)
 103     write_bus(bus, p, ifaces)
 104     write_instances(idef, p, ifaces)
 105     write_slow(slow, slowt, p, ifaces, iocells)
 106
 107
 108 def write_slow(slow, template, p, ifaces, iocells):
 109     """ write out the slow_peripherals.bsv file.
 110         joins all the peripherals together into one AXI Lite interface
 111     """
 112     with open(template) as bsv_file:
 113         template = bsv_file.read()
 114     imports = ifaces.slowimport()
 115     ifdecl = ifaces.slowifdeclmux()
 116     regdef = ifaces.axi_reg_def()
 117     slavedecl = ifaces.axi_slave_idx()
 118     fnaddrmap = ifaces.axi_addr_map()
 119     mkslow = ifaces.mkslow_peripheral()
 120     mkcon = ifaces.mk_connection()
 121     mkcellcon = ifaces.mk_cellconn()
 122     pincon = ifaces.mk_pincon()
 123     inst = ifaces.slowifinstance()
 124     with open(slow, "w") as bsv_file:
 125         bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
 126                                        fnaddrmap, mkslow, mkcon, mkcellcon,
 127                                        pincon, inst))
 128
 129
 130 def write_bus(bus, p, ifaces):
 131     # package and interface declaration followed by
 132     # the generic io_cell definition
 133     with open(bus, "w") as bsv_file:
 134         ifaces.busfmt(bsv_file)
 135
 136
 137 def write_pmp(pmp, p, ifaces, iocells):
 138     # package and interface declaration followed by
 139     # the generic io_cell definition
 140     with open(pmp, "w") as bsv_file:
 141         bsv_file.write(header)
 142
 143         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 144         bsv_file.write('''\
 145    interface MuxSelectionLines;
 146
 147       // declare the method which will capture the user pin-mux
 148       // selection values.The width of the input is dependent on the number
 149       // of muxes happening per IO. For now we have a generalized width
 150       // where each IO will have the same number of muxes.''')
 151
 152         for cell in p.muxed_cells:
 153             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 154
 155         bsv_file.write("\n      endinterface\n")
 156
 157         bsv_file.write('''
 158
 159       interface IOCellSide;
 160       // declare the interface to the IO cells.
 161       // Each IO cell will have 1 input field (output from pin mux)
 162       // and an output and out-enable field (input to pinmux)''')
 163
 164         # == create method definitions for all iocell interfaces ==#
 165         iocells.ifacefmt(bsv_file)
 166
 167         # ===== finish interface definition and start module definition=======
 168         bsv_file.write("\n      endinterface\n")
 169
 170         # ===== io cell definition =======
 171         bsv_file.write('''
 172
 173       interface PeripheralSide;
 174       // declare the interface to the peripherals
 175       // Each peripheral's function will be either an input, output
 176       // or be bi-directional.  an input field will be an output from the
 177       // peripheral and an output field will be an input to the peripheral.
 178       // Bi-directional functions also have an output-enable (which
 179       // again comes *in* from the peripheral)''')
 180         # ==============================================================
 181
 182         # == create method definitions for all peripheral interfaces ==#
 183         ifaces.ifacefmt(bsv_file)
 184         bsv_file.write("\n      endinterface\n")
 185
 186         # ===== finish interface definition and start module definition=======
 187         bsv_file.write('''
 188
 189    interface Ifc_pinmux;
 190       // this interface controls how each IO cell is routed.  setting
 191       // any given IO cell's mux control value will result in redirection
 192       // of not just the input or output to different peripheral functions
 193       // but also the *direction* control - if appropriate - as well.
 194       interface MuxSelectionLines mux_lines;
 195
 196       // this interface contains the inputs, outputs and direction-control
 197       // lines for all peripherals.  GPIO is considered to also be just
 198       // a peripheral because it also has in, out and direction-control.
 199       interface PeripheralSide peripheral_side;
 200
 201       // this interface is to be linked to the individual IO cells.
 202       // if looking at a "non-muxed" GPIO design, basically the
 203       // IO cell input, output and direction-control wires are cut
 204       // (giving six pairs of dangling wires, named left and right)
 205       // these iocells are routed in their place on one side ("left")
 206       // and the matching *GPIO* peripheral interfaces in/out/dir
 207       // connect to the OTHER side ("right").  the result is that
 208       // the muxer settings end up controlling the routing of where
 209       // the I/O from the IOcell actually goes.
 210       interface IOCellSide iocell_side;
 211    endinterface
 212    (*synthesize*)
 213    module mkpinmux(Ifc_pinmux);
 214 ''')
 215         # ====================================================================
 216
 217         # ======================= create wire and registers =================#
 218         bsv_file.write('''
 219       // the followins wires capture the pin-mux selection
 220       // values for each mux assigned to a CELL
 221 ''')
 222         for cell in p.muxed_cells:
 223             bsv_file.write(mux_interface.wirefmt(
 224                 cell[0], cell_bit_width))
 225
 226         iocells.wirefmt(bsv_file)
 227         ifaces.wirefmt(bsv_file)
 228
 229         bsv_file.write("\n")
 230         # ====================================================================
 231         # ========================= Actual pinmuxing ========================#
 232         bsv_file.write('''
 233       /*====== This where the muxing starts for each io-cell======*/
 234       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 235 ''')
 236         bsv_file.write(p.pinmux)
 237         bsv_file.write('''
 238       /*============================================================*/
 239 ''')
 240         # ====================================================================
 241         # ================= interface definitions for each method =============#
 242         bsv_file.write('''
 243     interface mux_lines = interface MuxSelectionLines
 244 ''')
 245         for cell in p.muxed_cells:
 246             bsv_file.write(
 247                 mux_interface.ifacedef(
 248                     cell[0], cell_bit_width))
 249         bsv_file.write("\n    endinterface;")
 250
 251         bsv_file.write('''
 252     interface iocell_side = interface IOCellSide
 253 ''')
 254         iocells.ifacedef(bsv_file)
 255         bsv_file.write("\n     endinterface;")
 256
 257         bsv_file.write('''
 258     interface peripheral_side = interface PeripheralSide
 259 ''')
 260         ifaces.ifacedef(bsv_file)
 261         bsv_file.write("\n     endinterface;")
 262
 263         bsv_file.write(footer)
 264         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 265         # ======================================================================
 266
 267
 268 def write_ptp(ptp, p, ifaces):
 269     with open(ptp, 'w') as bsv_file:
 270         bsv_file.write(copyright + '''
 271 package PinTop;
 272     import pinmux::*;
 273     interface Ifc_PintTop;
 274         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 275         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 276         interface PeripheralSide peripheral_side;
 277     endinterface
 278
 279     module mkPinTop(Ifc_PintTop);
 280         // instantiate the pin-mux module here
 281         Ifc_pinmux pinmux <-mkpinmux;
 282
 283         // declare the registers which will be used to mux the IOs
 284 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 285
 286         cell_bit_width = str(p.cell_bitwidth)
 287         for cell in p.muxed_cells:
 288             bsv_file.write('''
 289                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 290                 cell_bit_width, cell[0]))
 291
 292         bsv_file.write('''
 293         // rule to connect the registers to the selection lines of the
 294         // pin-mux module
 295         rule connect_selection_registers;''')
 296
 297         for cell in p.muxed_cells:
 298             bsv_file.write('''
 299           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 300
 301         bsv_file.write('''
 302         endrule
 303         // method definitions for the write user interface
 304         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 305           Bool err=False;
 306           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 307                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 308         index = 0
 309         for cell in p.muxed_cells:
 310             bsv_file.write('''
 311             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 312             index = index + 1
 313
 314         bsv_file.write('''
 315             default: err=True;
 316           endcase
 317           return err;
 318         endmethod''')
 319
 320         bsv_file.write('''
 321         // method definitions for the read user interface
 322         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 323           Bool err=False;
 324           Bit#(32) data=0;
 325           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 326                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 327         index = 0
 328         for cell in p.muxed_cells:
 329             bsv_file.write('''
 330                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 331             index = index + 1
 332
 333         bsv_file.write('''
 334             default:err=True;
 335           endcase
 336           return tuple2(err,data);
 337         endmethod
 338         interface peripheral_side=pinmux.peripheral_side;
 339     endmodule
 340 endpackage
 341 ''')
 342
 343
 344 def write_bvp(bvp, p, ifaces):
 345     # ######## Generate bus transactors ################
 346     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 347               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 348     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 349         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 350
 351     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 352     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 353     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 354               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 355     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 356         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 357     with open(bvp, 'w') as bsv_file:
 358         # assume here that all muxes have a 1:1 gpio
 359         cfg = []
 360         decl = []
 361         idec = []
 362         iks = sorted(ifaces.keys())
 363         for iname in iks:
 364             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 365                 continue
 366             bank = iname[4:]
 367             ifc = ifaces[iname]
 368             npins = len(ifc.pinspecs)
 369             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 370                                       0,  # USERSPACE
 371                                       bank, npins))
 372             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 373                                      0,  # USERSPACE
 374                                      bank, npins))
 375             decl.append(gpiodec.format(npins, bank))
 376             decl.append(muxdec .format(npins, bank))
 377             idec.append(gpioifc.format(bank))
 378             idec.append(muxifc.format(bank))
 379         print dir(ifaces)
 380         print ifaces.items()
 381         print dir(ifaces['gpioa'])
 382         print ifaces['gpioa'].pinspecs
 383         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 384         gpiocfg = '\n'.join(cfg)
 385         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 386     # ##################################################
 387
 388
 389 def write_instances(idef, p, ifaces):
 390     with open(idef, 'w') as bsv_file:
 391         txt = '''\
 392 `define ADDR {0}
 393 `define PADDR {0}
 394 `define DATA {1}
 395 `define Reg_width {1}
 396 `define USERSPACE 0
 397
 398 // TODO: work out if these are needed
 399 `define PWM_AXI4Lite
 400 `define PRFDEPTH 6
 401 `define VADDR 39
 402 `define DCACHE_BLOCK_SIZE 4
 403 `define DCACHE_WORD_SIZE 8
 404 `define PERFMONITORS                            64
 405 `define DCACHE_WAYS 4
 406 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 407 `define PLIC
 408         `define PLICBase                'h0c000000
 409         `define PLICEnd         'h10000000
 410 `define INTERRUPT_PINS 64
 411
 412 `define BAUD_RATE 130
 413 `ifdef simulate
 414   `define BAUD_RATE 5 //130 //
 415 `endif
 416 '''
 417         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))