src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 '''
  43 footer = '''
  44    endmodule
  45 endpackage
  46 '''
  47
  48
  49 def pinmuxgen(pth=None, verify=True):
  50     """ populating the file with the code
  51     """
  52
  53     p = Parse(pth, verify)
  54     iocells = Interfaces()
  55     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  56     ifaces = Interfaces(pth)
  57     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  58     init(p, ifaces)
  59
  60     bp = 'bsv_src'
  61     if pth:
  62         bp = os.path.join(pth, bp)
  63     if not os.path.exists(bp):
  64         os.makedirs(bp)
  65     bl = os.path.join(bp, 'bsv_lib')
  66     if not os.path.exists(bl):
  67         os.makedirs(bl)
  68
  69     cwd = os.path.split(__file__)[0]
  70
  71     # copy over template and library files
  72     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  73                     os.path.join(bp, 'Makefile'))
  74     cwd = os.path.join(cwd, 'bsv_lib')
  75     for fname in [ ]:
  76         shutil.copyfile(os.path.join(cwd, fname),
  77                         os.path.join(bl, fname))
  78
  79     bus = os.path.join(bp, 'busenable.bsv')
  80     pmp = os.path.join(bp, 'pinmux.bsv')
  81     ptp = os.path.join(bp, 'PinTop.bsv')
  82     bvp = os.path.join(bp, 'bus.bsv')
  83     idef = os.path.join(bp, 'instance_defines.bsv')
  84     slow = os.path.join(bp, 'slow_peripherals.bsv')
  85     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  86
  87     write_pmp(pmp, p, ifaces, iocells)
  88     write_ptp(ptp, p, ifaces)
  89     write_bvp(bvp, p, ifaces)
  90     write_bus(bus, p, ifaces)
  91     write_instances(idef, p, ifaces)
  92     write_slow(slow, slowt, p, ifaces, iocells)
  93
  94
  95 def write_slow(slow, template, p, ifaces, iocells):
  96     """ write out the slow_peripherals.bsv file.
  97         joins all the peripherals together into one AXI Lite interface
  98     """
  99     with open(template) as bsv_file:
 100         template = bsv_file.read()
 101     imports = ifaces.slowimport()
 102     ifdecl = ifaces.slowifdeclmux()
 103     regdef = ifaces.axi_reg_def()
 104     slavedecl = ifaces.axi_slave_idx()
 105     fnaddrmap = ifaces.axi_addr_map()
 106     mkslow = ifaces.mkslow_peripheral()
 107     mkcon = ifaces.mk_connection()
 108     mkcellcon = ifaces.mk_cellconn()
 109     pincon = ifaces.mk_pincon()
 110     inst = ifaces.slowifinstance()
 111     mkplic = ifaces.mk_plic()
 112     numsloirqs = ifaces.mk_sloirqsdef()
 113     ifacedef = ifaces.mk_ext_ifacedef()
 114     ifacedef = ifaces.mk_ext_ifacedef()
 115     with open(slow, "w") as bsv_file:
 116         bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
 117                                        fnaddrmap, mkslow, mkcon, mkcellcon,
 118                                        pincon, inst, mkplic,
 119                                        numsloirqs, ifacedef))
 120
 121
 122 def write_bus(bus, p, ifaces):
 123     # package and interface declaration followed by
 124     # the generic io_cell definition
 125     with open(bus, "w") as bsv_file:
 126         ifaces.busfmt(bsv_file)
 127
 128
 129 def write_pmp(pmp, p, ifaces, iocells):
 130     # package and interface declaration followed by
 131     # the generic io_cell definition
 132     with open(pmp, "w") as bsv_file:
 133         bsv_file.write(header)
 134
 135         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 136         bsv_file.write('''\
 137    interface MuxSelectionLines;
 138
 139       // declare the method which will capture the user pin-mux
 140       // selection values.The width of the input is dependent on the number
 141       // of muxes happening per IO. For now we have a generalized width
 142       // where each IO will have the same number of muxes.''')
 143
 144         for cell in p.muxed_cells:
 145             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 146
 147         bsv_file.write("\n      endinterface\n")
 148
 149         bsv_file.write('''
 150
 151       interface IOCellSide;
 152       // declare the interface to the IO cells.
 153       // Each IO cell will have 1 input field (output from pin mux)
 154       // and an output and out-enable field (input to pinmux)''')
 155
 156         # == create method definitions for all iocell interfaces ==#
 157         iocells.ifacefmt(bsv_file)
 158
 159         # ===== finish interface definition and start module definition=======
 160         bsv_file.write("\n      endinterface\n")
 161
 162         # ===== io cell definition =======
 163         bsv_file.write('''
 164
 165       interface PeripheralSide;
 166       // declare the interface to the peripherals
 167       // Each peripheral's function will be either an input, output
 168       // or be bi-directional.  an input field will be an output from the
 169       // peripheral and an output field will be an input to the peripheral.
 170       // Bi-directional functions also have an output-enable (which
 171       // again comes *in* from the peripheral)''')
 172         # ==============================================================
 173
 174         # == create method definitions for all peripheral interfaces ==#
 175         ifaces.ifacefmt(bsv_file)
 176         bsv_file.write("\n      endinterface\n")
 177
 178         # ===== finish interface definition and start module definition=======
 179         bsv_file.write('''
 180
 181    interface Ifc_pinmux;
 182       // this interface controls how each IO cell is routed.  setting
 183       // any given IO cell's mux control value will result in redirection
 184       // of not just the input or output to different peripheral functions
 185       // but also the *direction* control - if appropriate - as well.
 186       interface MuxSelectionLines mux_lines;
 187
 188       // this interface contains the inputs, outputs and direction-control
 189       // lines for all peripherals.  GPIO is considered to also be just
 190       // a peripheral because it also has in, out and direction-control.
 191       interface PeripheralSide peripheral_side;
 192
 193       // this interface is to be linked to the individual IO cells.
 194       // if looking at a "non-muxed" GPIO design, basically the
 195       // IO cell input, output and direction-control wires are cut
 196       // (giving six pairs of dangling wires, named left and right)
 197       // these iocells are routed in their place on one side ("left")
 198       // and the matching *GPIO* peripheral interfaces in/out/dir
 199       // connect to the OTHER side ("right").  the result is that
 200       // the muxer settings end up controlling the routing of where
 201       // the I/O from the IOcell actually goes.
 202       interface IOCellSide iocell_side;
 203    endinterface
 204    (*synthesize*)
 205    module mkpinmux(Ifc_pinmux);
 206 ''')
 207         # ====================================================================
 208
 209         # ======================= create wire and registers =================#
 210         bsv_file.write('''
 211       // the followins wires capture the pin-mux selection
 212       // values for each mux assigned to a CELL
 213 ''')
 214         for cell in p.muxed_cells:
 215             bsv_file.write(mux_interface.wirefmt(
 216                 cell[0], cell_bit_width))
 217
 218         iocells.wirefmt(bsv_file)
 219         ifaces.wirefmt(bsv_file)
 220
 221         bsv_file.write("\n")
 222         # ====================================================================
 223         # ========================= Actual pinmuxing ========================#
 224         bsv_file.write('''
 225       /*====== This where the muxing starts for each io-cell======*/
 226       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 227 ''')
 228         bsv_file.write(p.pinmux)
 229         bsv_file.write('''
 230       /*============================================================*/
 231 ''')
 232         # ====================================================================
 233         # ================= interface definitions for each method =============#
 234         bsv_file.write('''
 235     interface mux_lines = interface MuxSelectionLines
 236 ''')
 237         for cell in p.muxed_cells:
 238             bsv_file.write(
 239                 mux_interface.ifacedef(
 240                     cell[0], cell_bit_width))
 241         bsv_file.write("\n    endinterface;")
 242
 243         bsv_file.write('''
 244     interface iocell_side = interface IOCellSide
 245 ''')
 246         iocells.ifacedef(bsv_file)
 247         bsv_file.write("\n     endinterface;")
 248
 249         bsv_file.write('''
 250     interface peripheral_side = interface PeripheralSide
 251 ''')
 252         ifaces.ifacedef(bsv_file)
 253         bsv_file.write("\n     endinterface;")
 254
 255         bsv_file.write(footer)
 256         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 257         # ======================================================================
 258
 259
 260 def write_ptp(ptp, p, ifaces):
 261     with open(ptp, 'w') as bsv_file:
 262         bsv_file.write(copyright + '''
 263 package PinTop;
 264     import pinmux::*;
 265     interface Ifc_PintTop;
 266         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 267         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 268         interface PeripheralSide peripheral_side;
 269     endinterface
 270
 271     module mkPinTop(Ifc_PintTop);
 272         // instantiate the pin-mux module here
 273         Ifc_pinmux pinmux <-mkpinmux;
 274
 275         // declare the registers which will be used to mux the IOs
 276 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 277
 278         cell_bit_width = str(p.cell_bitwidth)
 279         for cell in p.muxed_cells:
 280             bsv_file.write('''
 281                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 282                 cell_bit_width, cell[0]))
 283
 284         bsv_file.write('''
 285         // rule to connect the registers to the selection lines of the
 286         // pin-mux module
 287         rule connect_selection_registers;''')
 288
 289         for cell in p.muxed_cells:
 290             bsv_file.write('''
 291           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 292
 293         bsv_file.write('''
 294         endrule
 295         // method definitions for the write user interface
 296         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 297           Bool err=False;
 298           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 299                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 300         index = 0
 301         for cell in p.muxed_cells:
 302             bsv_file.write('''
 303             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 304             index = index + 1
 305
 306         bsv_file.write('''
 307             default: err=True;
 308           endcase
 309           return err;
 310         endmethod''')
 311
 312         bsv_file.write('''
 313         // method definitions for the read user interface
 314         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 315           Bool err=False;
 316           Bit#(32) data=0;
 317           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 318                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 319         index = 0
 320         for cell in p.muxed_cells:
 321             bsv_file.write('''
 322                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 323             index = index + 1
 324
 325         bsv_file.write('''
 326             default:err=True;
 327           endcase
 328           return tuple2(err,data);
 329         endmethod
 330         interface peripheral_side=pinmux.peripheral_side;
 331     endmodule
 332 endpackage
 333 ''')
 334
 335
 336 def write_bvp(bvp, p, ifaces):
 337     # ######## Generate bus transactors ################
 338     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 339               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 340     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 341         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 342
 343     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 344     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 345     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 346               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 347     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 348         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 349     with open(bvp, 'w') as bsv_file:
 350         # assume here that all muxes have a 1:1 gpio
 351         cfg = []
 352         decl = []
 353         idec = []
 354         iks = sorted(ifaces.keys())
 355         for iname in iks:
 356             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 357                 continue
 358             bank = iname[4:]
 359             ifc = ifaces[iname]
 360             npins = len(ifc.pinspecs)
 361             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 362                                       0,  # USERSPACE
 363                                       bank, npins))
 364             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 365                                      0,  # USERSPACE
 366                                      bank, npins))
 367             decl.append(gpiodec.format(npins, bank))
 368             decl.append(muxdec .format(npins, bank))
 369             idec.append(gpioifc.format(bank))
 370             idec.append(muxifc.format(bank))
 371         print dir(ifaces)
 372         print ifaces.items()
 373         print dir(ifaces['gpioa'])
 374         print ifaces['gpioa'].pinspecs
 375         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 376         gpiocfg = '\n'.join(cfg)
 377         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 378     # ##################################################
 379
 380
 381 def write_instances(idef, p, ifaces):
 382     with open(idef, 'w') as bsv_file:
 383         txt = '''\
 384 `define ADDR {0}
 385 `define PADDR {0}
 386 `define DATA {1}
 387 `define Reg_width {1}
 388 `define USERSPACE 0
 389
 390 // TODO: work out if these are needed
 391 `define PWM_AXI4Lite
 392 `define PRFDEPTH 6
 393 `define VADDR 39
 394 `define DCACHE_BLOCK_SIZE 4
 395 `define DCACHE_WORD_SIZE 8
 396 `define PERFMONITORS                            64
 397 `define DCACHE_WAYS 4
 398 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 399 `define PLIC
 400         `define PLICBase                'h0c000000
 401         `define PLICEnd         'h10000000
 402 `define INTERRUPT_PINS 64
 403
 404 `define BAUD_RATE 130
 405 `ifdef simulate
 406   `define BAUD_RATE 5 //130 //
 407 `endif
 408 '''
 409         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))