src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 '''
  43 footer = '''
  44    endmodule
  45 endpackage
  46 '''
  47
  48
  49 def pinmuxgen(pth=None, verify=True):
  50     """ populating the file with the code
  51     """
  52
  53     p = Parse(pth, verify)
  54     iocells = Interfaces()
  55     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  56     ifaces = Interfaces(pth)
  57     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  58     init(p, ifaces)
  59
  60     bp = 'bsv_src'
  61     if pth:
  62         bp = os.path.join(pth, bp)
  63     if not os.path.exists(bp):
  64         os.makedirs(bp)
  65     bl = os.path.join(bp, 'bsv_lib')
  66     if not os.path.exists(bl):
  67         os.makedirs(bl)
  68
  69     cwd = os.path.split(__file__)[0]
  70
  71     # copy over template and library files
  72     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  73                     os.path.join(bp, 'Makefile'))
  74     cwd = os.path.join(cwd, 'bsv_lib')
  75     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
  76         shutil.copyfile(os.path.join(cwd, fname),
  77                         os.path.join(bl, fname))
  78
  79     bus = os.path.join(bp, 'busenable.bsv')
  80     pmp = os.path.join(bp, 'pinmux.bsv')
  81     ptp = os.path.join(bp, 'PinTop.bsv')
  82     bvp = os.path.join(bp, 'bus.bsv')
  83
  84     write_pmp(pmp, p, ifaces, iocells)
  85     write_ptp(ptp, p, ifaces)
  86     write_bvp(bvp, p, ifaces)
  87     write_bus(bus, p, ifaces)
  88
  89
  90 def write_bus(bus, p, ifaces):
  91     # package and interface declaration followed by
  92     # the generic io_cell definition
  93     with open(bus, "w") as bsv_file:
  94         ifaces.busfmt(bsv_file)
  95
  96
  97 def write_pmp(pmp, p, ifaces, iocells):
  98     # package and interface declaration followed by
  99     # the generic io_cell definition
 100     with open(pmp, "w") as bsv_file:
 101         bsv_file.write(header)
 102
 103         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 104         bsv_file.write('''\
 105    interface MuxSelectionLines;
 106
 107       // declare the method which will capture the user pin-mux
 108       // selection values.The width of the input is dependent on the number
 109       // of muxes happening per IO. For now we have a generalized width
 110       // where each IO will have the same number of muxes.''')
 111
 112         for cell in p.muxed_cells:
 113             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 114
 115         bsv_file.write("\n      endinterface\n")
 116
 117         bsv_file.write('''
 118
 119       interface PeripheralSide;
 120       // declare the interface to the peripherals
 121       // Each peripheral's function will be either an input, output
 122       // or be bi-directional.  an input field will be an output from the
 123       // peripheral and an output field will be an input to the peripheral.
 124       // Bi-directional functions also have an output-enable (which
 125       // again comes *in* from the peripheral)''')
 126         # ==============================================================
 127
 128         # == create method definitions for all peripheral interfaces ==#
 129         iocells.ifacefmt(bsv_file)
 130
 131         # ===== finish interface definition and start module definition=======
 132         bsv_file.write("\n      endinterface\n")
 133
 134         # ===== io cell definition =======
 135         bsv_file.write('''
 136
 137       interface IOCellSide;
 138       // declare the interface to the IO cells.
 139       // Each IO cell will have 1 input field (output from pin mux)
 140       // and an output and out-enable field (input to pinmux)''')
 141
 142         # == create method definitions for all iocell interfaces ==#
 143         ifaces.ifacefmt(bsv_file)
 144         bsv_file.write("\n      endinterface\n")
 145
 146         # ===== finish interface definition and start module definition=======
 147         bsv_file.write('''
 148
 149    interface Ifc_pinmux;
 150       // this interface controls how each IO cell is routed.  setting
 151       // any given IO cell's mux control value will result in redirection
 152       // of not just the input or output to different peripheral functions
 153       // but also the *direction* control - if appropriate - as well.
 154       interface MuxSelectionLines mux_lines;
 155
 156       // this interface contains the inputs, outputs and direction-control
 157       // lines for all peripherals.  GPIO is considered to also be just
 158       // a peripheral because it also has in, out and direction-control.
 159       interface PeripheralSide peripheral_side;
 160
 161       // this interface is to be linked to the individual IO cells.
 162       // if looking at a "non-muxed" GPIO design, basically the
 163       // IO cell input, output and direction-control wires are cut
 164       // (giving six pairs of dangling wires, named left and right)
 165       // these iocells are routed in their place on one side ("left")
 166       // and the matching *GPIO* peripheral interfaces in/out/dir
 167       // connect to the OTHER side ("right").
 168       interface IOCellSide iocell_side;
 169    endinterface
 170    (*synthesize*)
 171    module mkpinmux(Ifc_pinmux);
 172 ''')
 173         # ====================================================================
 174
 175         # ======================= create wire and registers =================#
 176         bsv_file.write('''
 177       // the followins wires capture the pin-mux selection
 178       // values for each mux assigned to a CELL
 179 ''')
 180         for cell in p.muxed_cells:
 181             bsv_file.write(mux_interface.wirefmt(
 182                 cell[0], cell_bit_width))
 183
 184         iocells.wirefmt(bsv_file)
 185         ifaces.wirefmt(bsv_file)
 186
 187         bsv_file.write("\n")
 188         # ====================================================================
 189         # ========================= Actual pinmuxing ========================#
 190         bsv_file.write('''
 191       /*====== This where the muxing starts for each io-cell======*/
 192 ''')
 193         bsv_file.write(p.pinmux)
 194         bsv_file.write('''
 195       /*============================================================*/
 196 ''')
 197         # ====================================================================
 198         # ================= interface definitions for each method =============#
 199         bsv_file.write('''
 200     interface mux_lines = interface MuxSelectionLines
 201 ''')
 202         for cell in p.muxed_cells:
 203             bsv_file.write(
 204                 mux_interface.ifacedef(
 205                     cell[0], cell_bit_width))
 206         bsv_file.write("\n    endinterface;")
 207
 208         bsv_file.write('''
 209     interface iocell_side = interface IOCellSide
 210 ''')
 211         iocells.ifacedef(bsv_file)
 212         bsv_file.write("\n     endinterface;")
 213
 214         bsv_file.write('''
 215     interface peripheral_side = interface PeripheralSide
 216 ''')
 217         ifaces.ifacedef(bsv_file)
 218         bsv_file.write("\n     endinterface;")
 219
 220
 221         bsv_file.write(footer)
 222         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 223         # ======================================================================
 224
 225
 226 def write_ptp(ptp, p, ifaces):
 227     with open(ptp, 'w') as bsv_file:
 228         bsv_file.write(copyright + '''
 229 package PinTop;
 230     import pinmux::*;
 231     interface Ifc_PintTop;
 232         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 233         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 234         interface PeripheralSide peripheral_side;
 235     endinterface
 236
 237     module mkPinTop(Ifc_PintTop);
 238         // instantiate the pin-mux module here
 239         Ifc_pinmux pinmux <-mkpinmux;
 240
 241         // declare the registers which will be used to mux the IOs
 242 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 243
 244         cell_bit_width = str(p.cell_bitwidth)
 245         for cell in p.muxed_cells:
 246             bsv_file.write('''
 247                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 248                 cell_bit_width, cell[0]))
 249
 250         bsv_file.write('''
 251         // rule to connect the registers to the selection lines of the
 252         // pin-mux module
 253         rule connect_selection_registers;''')
 254
 255         for cell in p.muxed_cells:
 256             bsv_file.write('''
 257           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 258
 259         bsv_file.write('''
 260         endrule
 261         // method definitions for the write user interface
 262         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 263           Bool err=False;
 264           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 265                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 266         index = 0
 267         for cell in p.muxed_cells:
 268             bsv_file.write('''
 269             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 270             index = index + 1
 271
 272         bsv_file.write('''
 273             default: err=True;
 274           endcase
 275           return err;
 276         endmethod''')
 277
 278         bsv_file.write('''
 279         // method definitions for the read user interface
 280         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 281           Bool err=False;
 282           Bit#(32) data=0;
 283           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 284                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 285         index = 0
 286         for cell in p.muxed_cells:
 287             bsv_file.write('''
 288                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 289             index = index + 1
 290
 291         bsv_file.write('''
 292             default:err=True;
 293           endcase
 294           return tuple2(err,data);
 295         endmethod
 296         interface peripheral_side=pinmux.peripheral_side;
 297     endmodule
 298 endpackage
 299 ''')
 300
 301
 302 def write_bvp(bvp, p, ifaces):
 303     # ######## Generate bus transactors ################
 304     with open(bvp, 'w') as bsv_file:
 305         bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 306     # ##################################################