1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
52 def pinmuxgen(pth
=None, verify
=True):
53 """ populating the file with the code
56 p
= Parse(pth
, verify
)
57 iocells
= Interfaces()
58 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
59 ifaces
= Interfaces(pth
)
60 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
65 bp
= os
.path
.join(pth
, bp
)
66 if not os
.path
.exists(bp
):
68 bl
= os
.path
.join(bp
, 'bsv_lib')
69 if not os
.path
.exists(bl
):
72 cwd
= os
.path
.split(__file__
)[0]
74 # copy over template and library files
75 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
76 os
.path
.join(bp
, 'Makefile'))
77 cwd
= os
.path
.join(cwd
, 'bsv_lib')
79 shutil
.copyfile(os
.path
.join(cwd
, fname
),
80 os
.path
.join(bl
, fname
))
82 bus
= os
.path
.join(bp
, 'busenable.bsv')
83 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
84 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
85 bvp
= os
.path
.join(bp
, 'bus.bsv')
86 idef
= os
.path
.join(bp
, 'instance_defines.bsv')
87 slow
= os
.path
.join(bp
, 'slow_peripherals.bsv')
88 slowt
= os
.path
.join(cwd
, 'slow_peripherals_template.bsv')
89 soc
= os
.path
.join(bp
, 'soc.bsv')
90 soct
= os
.path
.join(cwd
, 'soc_template.bsv')
92 write_pmp(pmp
, p
, ifaces
, iocells
)
93 write_ptp(ptp
, p
, ifaces
)
94 write_bvp(bvp
, p
, ifaces
)
95 write_bus(bus
, p
, ifaces
)
96 write_instances(idef
, p
, ifaces
)
97 write_slow(slow
, slowt
, p
, ifaces
, iocells
)
98 write_soc(soc
, soct
, p
, ifaces
, iocells
)
101 def write_slow(slow
, slowt
, p
, ifaces
, iocells
):
102 """ write out the slow_peripherals.bsv file.
103 joins all the peripherals together into one AXI Lite interface
105 with
open(slowt
) as bsv_file
:
106 slowt
= bsv_file
.read()
107 imports
= ifaces
.slowimport()
108 ifdecl
= ifaces
.slowifdeclmux() + '\n' + ifaces
.extifdecl()
109 regdef
= ifaces
.axi_reg_def()
110 slavedecl
= ifaces
.axi_slave_idx()
111 fnaddrmap
= ifaces
.axi_addr_map()
112 mkslow
= ifaces
.mkslow_peripheral()
113 mkcon
= ifaces
.mk_connection()
114 mkcellcon
= ifaces
.mk_cellconn()
115 pincon
= ifaces
.mk_pincon()
116 inst
= ifaces
.extifinstance()
117 mkplic
= ifaces
.mk_plic()
118 numsloirqs
= ifaces
.mk_sloirqsdef()
119 ifacedef
= ifaces
.mk_ext_ifacedef()
120 ifacedef
= ifaces
.mk_ext_ifacedef()
121 with
open(slow
, "w") as bsv_file
:
122 bsv_file
.write(slowt
.format(imports
, ifdecl
, regdef
, slavedecl
,
123 fnaddrmap
, mkslow
, mkcon
, mkcellcon
,
124 pincon
, inst
, mkplic
,
125 numsloirqs
, ifacedef
))
127 def write_soc(soc
, soct
, p
, ifaces
, iocells
):
128 """ write out the soc.bsv file.
129 joins all the peripherals together as AXI Masters
131 ifaces
.fastbusmode
= True # side-effects... shouldn't really do this
132 with
open(soct
) as bsv_file
:
133 soct
= bsv_file
.read()
134 imports
= ifaces
.slowimport()
135 ifdecl
= "" #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
136 regdef
= ifaces
.axi_reg_def()
137 slavedecl
= ifaces
.axi_fastslave_idx()
138 fnaddrmap
= ifaces
.axi_addr_map()
139 mkfast
= ifaces
.mkfast_peripheral()
140 mkcon
= ifaces
.mk_connection()
141 mkcellcon
= ifaces
.mk_cellconn()
142 pincon
= ifaces
.mk_pincon()
143 inst
= ifaces
.extifinstance()
144 mkplic
= ifaces
.mk_plic()
145 numsloirqs
= ifaces
.mk_sloirqsdef()
146 ifacedef
= ifaces
.mk_ext_ifacedef()
147 ifacedef
= ifaces
.mk_ext_ifacedef()
148 with
open(soc
, "w") as bsv_file
:
149 bsv_file
.write(soct
.format(imports
, ifdecl
, mkfast
,
151 #'', '' #regdef, slavedecl,
152 #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
153 #pincon, inst, mkplic,
154 #numsloirqs, ifacedef))
158 def write_bus(bus
, p
, ifaces
):
159 # package and interface declaration followed by
160 # the generic io_cell definition
161 with
open(bus
, "w") as bsv_file
:
162 ifaces
.busfmt(bsv_file
)
165 def write_pmp(pmp
, p
, ifaces
, iocells
):
166 # package and interface declaration followed by
167 # the generic io_cell definition
168 with
open(pmp
, "w") as bsv_file
:
169 bsv_file
.write(header
)
171 cell_bit_width
= 'Bit#(%d)' % p
.cell_bitwidth
173 (*always_ready,always_enabled*)
174 interface MuxSelectionLines;
176 // declare the method which will capture the user pin-mux
177 // selection values.The width of the input is dependent on the number
178 // of muxes happening per IO. For now we have a generalized width
179 // where each IO will have the same number of muxes.''')
181 for cell
in p
.muxed_cells
:
182 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cell_bit_width
))
184 bsv_file
.write("\n endinterface\n")
188 interface IOCellSide;
189 // declare the interface to the IO cells.
190 // Each IO cell will have 1 input field (output from pin mux)
191 // and an output and out-enable field (input to pinmux)''')
193 # == create method definitions for all iocell interfaces ==#
194 iocells
.ifacefmt(bsv_file
)
196 # ===== finish interface definition and start module definition=======
197 bsv_file
.write("\n endinterface\n")
199 ifaces
.ifacepfmt(bsv_file
)
200 # ===== io cell definition =======
202 (*always_ready,always_enabled*)
203 interface PeripheralSide;
204 // declare the interface to the peripherals
205 // Each peripheral's function will be either an input, output
206 // or be bi-directional. an input field will be an output from the
207 // peripheral and an output field will be an input to the peripheral.
208 // Bi-directional functions also have an output-enable (which
209 // again comes *in* from the peripheral)''')
210 # ==============================================================
212 # == create method definitions for all peripheral interfaces ==#
213 ifaces
.ifacefmt2(bsv_file
)
214 bsv_file
.write("\n endinterface\n")
216 # ===== finish interface definition and start module definition=======
219 interface Ifc_pinmux;
220 // this interface controls how each IO cell is routed. setting
221 // any given IO cell's mux control value will result in redirection
222 // of not just the input or output to different peripheral functions
223 // but also the *direction* control - if appropriate - as well.
224 interface MuxSelectionLines mux_lines;
226 // this interface contains the inputs, outputs and direction-control
227 // lines for all peripherals. GPIO is considered to also be just
228 // a peripheral because it also has in, out and direction-control.
229 interface PeripheralSide peripheral_side;
231 // this interface is to be linked to the individual IO cells.
232 // if looking at a "non-muxed" GPIO design, basically the
233 // IO cell input, output and direction-control wires are cut
234 // (giving six pairs of dangling wires, named left and right)
235 // these iocells are routed in their place on one side ("left")
236 // and the matching *GPIO* peripheral interfaces in/out/dir
237 // connect to the OTHER side ("right"). the result is that
238 // the muxer settings end up controlling the routing of where
239 // the I/O from the IOcell actually goes.
240 interface IOCellSide iocell_side;
244 module mkpinmux(Ifc_pinmux);
246 # ====================================================================
248 # ======================= create wire and registers =================#
250 // the followins wires capture the pin-mux selection
251 // values for each mux assigned to a CELL
253 for cell
in p
.muxed_cells
:
254 bsv_file
.write(mux_interface
.wirefmt(
255 cell
[0], cell_bit_width
))
257 iocells
.wirefmt(bsv_file
)
258 ifaces
.wirefmt(bsv_file
)
261 # ====================================================================
262 # ========================= Actual pinmuxing ========================#
264 /*====== This where the muxing starts for each io-cell======*/
265 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
267 bsv_file
.write(p
.pinmux
)
269 /*============================================================*/
271 # ====================================================================
272 # ================= interface definitions for each method =============#
274 interface mux_lines = interface MuxSelectionLines
276 for cell
in p
.muxed_cells
:
278 mux_interface
.ifacedef(
279 cell
[0], cell_bit_width
))
280 bsv_file
.write("\n endinterface;")
284 interface iocell_side = interface IOCellSide
286 iocells
.ifacedef(bsv_file
)
287 bsv_file
.write("\n endinterface;")
291 interface peripheral_side = interface PeripheralSide
293 ifaces
.ifacedef2(bsv_file
)
294 bsv_file
.write("\n endinterface;")
296 bsv_file
.write(footer
)
297 print("BSV file successfully generated: bsv_src/pinmux.bsv")
298 # ======================================================================
301 def write_ptp(ptp
, p
, ifaces
):
302 with
open(ptp
, 'w') as bsv_file
:
303 bsv_file
.write(copyright
+ '''
306 interface Ifc_PintTop;
307 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
308 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
309 interface PeripheralSide peripheral_side;
312 module mkPinTop(Ifc_PintTop);
313 // instantiate the pin-mux module here
314 Ifc_pinmux pinmux <-mkpinmux;
316 // declare the registers which will be used to mux the IOs
317 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
319 cell_bit_width
= str(p
.cell_bitwidth
)
320 for cell
in p
.muxed_cells
:
322 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
323 cell_bit_width
, cell
[0]))
326 // rule to connect the registers to the selection lines of the
328 rule connect_selection_registers;''')
330 for cell
in p
.muxed_cells
:
332 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
336 // method definitions for the write user interface
337 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
339 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
340 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
342 for cell
in p
.muxed_cells
:
344 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
354 // method definitions for the read user interface
355 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
358 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
359 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
361 for cell
in p
.muxed_cells
:
363 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
369 return tuple2(err,data);
371 interface peripheral_side=pinmux.peripheral_side;
377 def write_bvp(bvp
, p
, ifaces
):
378 # ######## Generate bus transactors ################
379 gpiocfg
= '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
380 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
381 muxcfg
= '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
382 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
384 gpiodec
= '\tGPIO#({0}) mygpio{1} <- mkgpio();'
385 muxdec
= '\tMUX#({0}) mymux{1} <- mkmux();'
386 gpioifc
= '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
387 '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
388 muxifc
= '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
389 '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
390 with
open(bvp
, 'w') as bsv_file
:
391 # assume here that all muxes have a 1:1 gpio
395 iks
= sorted(ifaces
.keys())
397 if not iname
.startswith('gpio'): # TODO: declare other interfaces
401 npins
= len(ifc
.pinspecs
)
402 cfg
.append(gpiocfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
405 cfg
.append(muxcfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
408 decl
.append(gpiodec
.format(npins
, bank
))
409 decl
.append(muxdec
.format(npins
, bank
))
410 idec
.append(gpioifc
.format(bank
))
411 idec
.append(muxifc
.format(bank
))
414 print dir(ifaces
['gpioa'])
415 print ifaces
['gpioa'].pinspecs
416 gpiodecl
= '\n'.join(decl
) + '\n' + '\n'.join(idec
)
417 gpiocfg
= '\n'.join(cfg
)
418 bsv_file
.write(axi4_lite
.format(gpiodecl
, gpiocfg
))
419 # ##################################################
422 def write_instances(idef
, p
, ifaces
):
423 with
open(idef
, 'w') as bsv_file
:
428 `define Reg_width {1}
431 // TODO: work out if these are needed
435 `define DCACHE_BLOCK_SIZE 4
436 `define DCACHE_WORD_SIZE 8
437 `define PERFMONITORS 64
438 `define DCACHE_WAYS 4
439 `define DCACHE_TAG_BITS 20 // tag_bits = 52
441 `define PLICBase 'h0c000000
442 `define PLICEnd 'h10000000
443 `define INTERRUPT_PINS 64
445 `define BAUD_RATE 130
447 `define BAUD_RATE 5 //130 //
450 bsv_file
.write(txt
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))