src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     ptp = os.path.join(bp, 'PinTop.bsv')
  85     bvp = os.path.join(bp, 'bus.bsv')
  86     idef = os.path.join(bp, 'instance_defines.bsv')
  87     slow = os.path.join(bp, 'slow_peripherals.bsv')
  88     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  89     soc = os.path.join(bp, 'soc.bsv')
  90     soct = os.path.join(cwd, 'soc_template.bsv')
  91
  92     write_pmp(pmp, p, ifaces, iocells)
  93     write_ptp(ptp, p, ifaces)
  94     write_bvp(bvp, p, ifaces)
  95     write_bus(bus, p, ifaces)
  96     write_instances(idef, p, ifaces)
  97     write_slow(slow, slowt, p, ifaces, iocells)
  98     write_soc(soc, soct, p, ifaces, iocells)
  99
 100
 101 def write_slow(slow, slowt, p, ifaces, iocells):
 102     """ write out the slow_peripherals.bsv file.
 103         joins all the peripherals together into one AXI Lite interface
 104     """
 105     with open(slowt) as bsv_file:
 106         slowt = bsv_file.read()
 107     imports = ifaces.slowimport()
 108     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 109     regdef = ifaces.axi_reg_def()
 110     slavedecl = ifaces.axi_slave_idx()
 111     fnaddrmap = ifaces.axi_addr_map()
 112     mkslow = ifaces.mkslow_peripheral()
 113     mkcon = ifaces.mk_connection()
 114     mkcellcon = ifaces.mk_cellconn()
 115     pincon = ifaces.mk_pincon()
 116     inst = ifaces.extifinstance()
 117     mkplic = ifaces.mk_plic()
 118     numsloirqs = ifaces.mk_sloirqsdef()
 119     ifacedef = ifaces.mk_ext_ifacedef()
 120     ifacedef = ifaces.mk_ext_ifacedef()
 121     with open(slow, "w") as bsv_file:
 122         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 123                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 124                                     pincon, inst, mkplic,
 125                                     numsloirqs, ifacedef))
 126
 127 def write_soc(soc, soct, p, ifaces, iocells):
 128     """ write out the soc.bsv file.
 129         joins all the peripherals together as AXI Masters
 130     """
 131     ifaces.fastbusmode = True # side-effects... shouldn't really do this
 132     with open(soct) as bsv_file:
 133         soct = bsv_file.read()
 134     imports = ifaces.slowimport()
 135     ifdecl = ifaces.fastifdecl()
 136 #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 137     regdef = ifaces.axi_reg_def()
 138     slavedecl = ifaces.axi_fastslave_idx()
 139     mastdecl = ifaces.axi_master_idx()
 140     fnaddrmap = ifaces.axi_addr_map()
 141     mkfast = ifaces.mkfast_peripheral()
 142     mkcon = ifaces.mk_fast_connection()
 143     mkcellcon = ifaces.mk_cellconn()
 144     pincon = ifaces.mk_pincon()
 145     inst = ifaces.extfastifinstance()
 146     mkplic = ifaces.mk_plic()
 147     numsloirqs = ifaces.mk_sloirqsdef()
 148     ifacedef = ifaces.mk_ext_ifacedef()
 149     dma = ifaces.mk_dma_irq()
 150     with open(soc, "w") as bsv_file:
 151         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 152                             slavedecl, mastdecl, mkcon,
 153                             inst, dma,
 154                             #'', '' #regdef, slavedecl,
 155                             #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
 156                             #pincon, inst, mkplic,
 157                             #numsloirqs, ifacedef))
 158                                   ))
 159
 160
 161 def write_bus(bus, p, ifaces):
 162     # package and interface declaration followed by
 163     # the generic io_cell definition
 164     with open(bus, "w") as bsv_file:
 165         ifaces.busfmt(bsv_file)
 166
 167
 168 def write_pmp(pmp, p, ifaces, iocells):
 169     # package and interface declaration followed by
 170     # the generic io_cell definition
 171     with open(pmp, "w") as bsv_file:
 172         bsv_file.write(header)
 173
 174         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 175         bsv_file.write('''\
 176       (*always_ready,always_enabled*)
 177       interface MuxSelectionLines;
 178
 179       // declare the method which will capture the user pin-mux
 180       // selection values.The width of the input is dependent on the number
 181       // of muxes happening per IO. For now we have a generalized width
 182       // where each IO will have the same number of muxes.''')
 183
 184         for cell in p.muxed_cells:
 185             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 186
 187         bsv_file.write("\n      endinterface\n")
 188
 189         bsv_file.write('''
 190
 191       interface IOCellSide;
 192       // declare the interface to the IO cells.
 193       // Each IO cell will have 1 input field (output from pin mux)
 194       // and an output and out-enable field (input to pinmux)''')
 195
 196         # == create method definitions for all iocell interfaces ==#
 197         iocells.ifacefmt(bsv_file)
 198
 199         # ===== finish interface definition and start module definition=======
 200         bsv_file.write("\n      endinterface\n")
 201
 202         ifaces.ifacepfmt(bsv_file)
 203         # ===== io cell definition =======
 204         bsv_file.write('''
 205       (*always_ready,always_enabled*)
 206       interface PeripheralSide;
 207       // declare the interface to the peripherals
 208       // Each peripheral's function will be either an input, output
 209       // or be bi-directional.  an input field will be an output from the
 210       // peripheral and an output field will be an input to the peripheral.
 211       // Bi-directional functions also have an output-enable (which
 212       // again comes *in* from the peripheral)''')
 213         # ==============================================================
 214
 215         # == create method definitions for all peripheral interfaces ==#
 216         ifaces.ifacefmt2(bsv_file)
 217         bsv_file.write("\n      endinterface\n")
 218
 219         # ===== finish interface definition and start module definition=======
 220         bsv_file.write('''
 221
 222    interface Ifc_pinmux;
 223       // this interface controls how each IO cell is routed.  setting
 224       // any given IO cell's mux control value will result in redirection
 225       // of not just the input or output to different peripheral functions
 226       // but also the *direction* control - if appropriate - as well.
 227       interface MuxSelectionLines mux_lines;
 228
 229       // this interface contains the inputs, outputs and direction-control
 230       // lines for all peripherals.  GPIO is considered to also be just
 231       // a peripheral because it also has in, out and direction-control.
 232       interface PeripheralSide peripheral_side;
 233
 234       // this interface is to be linked to the individual IO cells.
 235       // if looking at a "non-muxed" GPIO design, basically the
 236       // IO cell input, output and direction-control wires are cut
 237       // (giving six pairs of dangling wires, named left and right)
 238       // these iocells are routed in their place on one side ("left")
 239       // and the matching *GPIO* peripheral interfaces in/out/dir
 240       // connect to the OTHER side ("right").  the result is that
 241       // the muxer settings end up controlling the routing of where
 242       // the I/O from the IOcell actually goes.
 243       interface IOCellSide iocell_side;
 244    endinterface
 245
 246    (*synthesize*)
 247    module mkpinmux(Ifc_pinmux);
 248 ''')
 249         # ====================================================================
 250
 251         # ======================= create wire and registers =================#
 252         bsv_file.write('''
 253       // the followins wires capture the pin-mux selection
 254       // values for each mux assigned to a CELL
 255 ''')
 256         for cell in p.muxed_cells:
 257             bsv_file.write(mux_interface.wirefmt(
 258                 cell[0], cell_bit_width))
 259
 260         iocells.wirefmt(bsv_file)
 261         ifaces.wirefmt(bsv_file)
 262
 263         bsv_file.write("\n")
 264         # ====================================================================
 265         # ========================= Actual pinmuxing ========================#
 266         bsv_file.write('''
 267       /*====== This where the muxing starts for each io-cell======*/
 268       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 269 ''')
 270         bsv_file.write(p.pinmux)
 271         bsv_file.write('''
 272       /*============================================================*/
 273 ''')
 274         # ====================================================================
 275         # ================= interface definitions for each method =============#
 276         bsv_file.write('''
 277     interface mux_lines = interface MuxSelectionLines
 278 ''')
 279         for cell in p.muxed_cells:
 280             bsv_file.write(
 281                 mux_interface.ifacedef(
 282                     cell[0], cell_bit_width))
 283         bsv_file.write("\n    endinterface;")
 284
 285         bsv_file.write('''
 286
 287     interface iocell_side = interface IOCellSide
 288 ''')
 289         iocells.ifacedef(bsv_file)
 290         bsv_file.write("\n     endinterface;")
 291
 292         bsv_file.write('''
 293
 294      interface peripheral_side = interface PeripheralSide
 295 ''')
 296         ifaces.ifacedef2(bsv_file)
 297         bsv_file.write("\n      endinterface;")
 298
 299         bsv_file.write(footer)
 300         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 301         # ======================================================================
 302
 303
 304 def write_ptp(ptp, p, ifaces):
 305     with open(ptp, 'w') as bsv_file:
 306         bsv_file.write(copyright + '''
 307 package PinTop;
 308     import pinmux::*;
 309     interface Ifc_PintTop;
 310         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 311         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 312         interface PeripheralSide peripheral_side;
 313     endinterface
 314
 315     module mkPinTop(Ifc_PintTop);
 316         // instantiate the pin-mux module here
 317         Ifc_pinmux pinmux <-mkpinmux;
 318
 319         // declare the registers which will be used to mux the IOs
 320 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 321
 322         cell_bit_width = str(p.cell_bitwidth)
 323         for cell in p.muxed_cells:
 324             bsv_file.write('''
 325                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 326                 cell_bit_width, cell[0]))
 327
 328         bsv_file.write('''
 329         // rule to connect the registers to the selection lines of the
 330         // pin-mux module
 331         rule connect_selection_registers;''')
 332
 333         for cell in p.muxed_cells:
 334             bsv_file.write('''
 335           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 336
 337         bsv_file.write('''
 338         endrule
 339         // method definitions for the write user interface
 340         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 341           Bool err=False;
 342           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 343                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 344         index = 0
 345         for cell in p.muxed_cells:
 346             bsv_file.write('''
 347             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 348             index = index + 1
 349
 350         bsv_file.write('''
 351             default: err=True;
 352           endcase
 353           return err;
 354         endmethod''')
 355
 356         bsv_file.write('''
 357         // method definitions for the read user interface
 358         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 359           Bool err=False;
 360           Bit#(32) data=0;
 361           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 362                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 363         index = 0
 364         for cell in p.muxed_cells:
 365             bsv_file.write('''
 366                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 367             index = index + 1
 368
 369         bsv_file.write('''
 370             default:err=True;
 371           endcase
 372           return tuple2(err,data);
 373         endmethod
 374         interface peripheral_side=pinmux.peripheral_side;
 375     endmodule
 376 endpackage
 377 ''')
 378
 379
 380 def write_bvp(bvp, p, ifaces):
 381     # ######## Generate bus transactors ################
 382     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 383               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 384     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 385         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 386
 387     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 388     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 389     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 390               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 391     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 392         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 393     with open(bvp, 'w') as bsv_file:
 394         # assume here that all muxes have a 1:1 gpio
 395         cfg = []
 396         decl = []
 397         idec = []
 398         iks = sorted(ifaces.keys())
 399         for iname in iks:
 400             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 401                 continue
 402             bank = iname[4:]
 403             ifc = ifaces[iname]
 404             npins = len(ifc.pinspecs)
 405             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 406                                       0,  # USERSPACE
 407                                       bank, npins))
 408             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 409                                      0,  # USERSPACE
 410                                      bank, npins))
 411             decl.append(gpiodec.format(npins, bank))
 412             decl.append(muxdec .format(npins, bank))
 413             idec.append(gpioifc.format(bank))
 414             idec.append(muxifc.format(bank))
 415         print dir(ifaces)
 416         print ifaces.items()
 417         print dir(ifaces['gpioa'])
 418         print ifaces['gpioa'].pinspecs
 419         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 420         gpiocfg = '\n'.join(cfg)
 421         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 422     # ##################################################
 423
 424
 425 def write_instances(idef, p, ifaces):
 426     with open(idef, 'w') as bsv_file:
 427         txt = '''\
 428 `define ADDR {0}
 429 `define PADDR {0}
 430 `define DATA {1}
 431 `define Reg_width {1}
 432 `define USERSPACE 0
 433
 434 // TODO: work out if these are needed
 435 `define PWM_AXI4Lite
 436 `define PRFDEPTH 6
 437 `define VADDR 39
 438 `define DCACHE_BLOCK_SIZE 4
 439 `define DCACHE_WORD_SIZE 8
 440 `define PERFMONITORS                            64
 441 `define DCACHE_WAYS 4
 442 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 443 `define PLIC
 444         `define PLICBase                'h0c000000
 445         `define PLICEnd         'h10000000
 446 `define INTERRUPT_PINS 64
 447
 448 `define BAUD_RATE 130
 449 `ifdef simulate
 450   `define BAUD_RATE 5 //130 //
 451 `endif
 452 '''
 453         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))